Analog Devices ADuC812 manual TF1, TR1, TF0, TR0, IE1, IT1, IE0, IT0

Page 31

ADuC812

TCON: Timer/Counter 0 and 1 Control Register

SFR Address

88H

Power-On Default Value

00H

Bit Addressable

Yes

TF1

TR1

TF0

TR0

IE11

IT11

IE01

IT01

NOTE

1These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins.

 

 

Table XVII. TCON SFR Bit Designations

 

 

 

Bit

Name

Description

 

 

 

7

TF1

Timer 1 Overflow Flag.

 

 

Set by hardware on a timer/counter 1 overflow.

 

 

Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine.

6

TR1

Timer 1 Run Control Bit.

 

 

Set by user to turn on timer/counter 1.

 

 

Cleared by user to turn off timer/counter 1.

5

TF0

Timer 0 Overflow Flag.

 

 

Set by hardware on a timer/counter 0 overflow.

 

 

Cleared by hardware when the PC vectors to the interrupt service routine.

4

TR0

Timer 0 Run Control Bit.

 

 

Set by user to turn on timer/counter 0.

 

 

Cleared by user to turn off timer/counter 0.

3

IE1

External Interrupt 1 (INT1) Flag.

 

 

Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1,

 

 

depending on bit IT1 state.

 

 

Cleared by hardware when the when the PC vectors to the interrupt service routine only if the

 

 

interrupt was transition-activated. If level-activated, the external requesting source controls the

 

 

request flag, rather than the on-chip hardware.

2

IT1

External Interrupt 1 (IE1) Trigger Type.

 

 

Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).

 

 

Cleared by software to specify level-sensitive detection (i.e., zero level).

1

IE0

External Interrupt 0 (INT0) Flag.

 

 

Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0,

 

 

depending on bit IT0 state.

 

 

Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt

 

 

was transition-activated. If level-activated, the external requesting source controls the request

 

 

flag, rather than the on-chip hardware.

0

IT0

External Interrupt 0 (IE0) Trigger Type.

 

 

Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition).

 

 

Cleared by software to specify level-sensitive detection (i.e., zero level).

 

 

 

Timer/Counter 0 and 1 Data Registers

Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register depending on the timer mode configuration.

TH0 and TL0

Timer 0 high byte and low byte.

SFR Address = 8CH, 8AH respectively.

TH1 and TL1

Timer 1 high byte and low byte.

SFR Address = 8DH, 8BH respectively.

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed byByte Program Sequence SFR areaNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2Rclk or Tclk CAP2 TR2 ModeOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B
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