Analog Devices ADuC812 manual F8H, Ooh, Ispi, Wcol, Spe, Spim, Cpol, Cpha

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ADuC812

SERIAL PERIPHERAL INTERFACE

The ADuC812 integrates a complete hardware Serial Peripheral Interface (SPI) on-chip. SPI is an industry standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex.

It should be noted that the SPI pins are shared with the I2C interface and therefore the user can only enable one or the other interface at any given time (see SPE in SPICON below). The SPI Port can be configured for Master or Slave operation and typically consists of four pins, namely:

MISO (Master In, Slave Out Data I/O Pin), Pin #19

The MISO (master in slave out) pin is configured as an input line in master mode and an output line in slave mode. The MISO line on the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as byte wide (8-bit) serial data, MSB first.

MOSI (Master Out, Slave In Pin), Pin #27

The MOSI (master out slave in) pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first.

SCLOCK (Serial Clock I/O Pin), Pin #26

The master serial clock (SCLOCK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines. A single data bit is transmitted and received in each SCLOCK period. Therefore, a byte is transmitted/received after eight SCLOCK periods. The

SCLOCK pin is configured as an output in master mode and as an input in slave mode. In master mode the bit-rate, polarity and phase of the clock are controlled by the CPOL, CPHA, SPR0 and SPR1 bits in the SPICON SFR (see Table XII). In slave mode the SPICON register will have to be configured with the phase and polarity (CPHA and CPOL) of the expected input clock. In both master and slave mode the data is transmitted on one edge of the SCLOCK signal and sampled on the other. It is important therefore that the CPHA and CPOL are configured the same for the master and slave devices.

SS(Slave Select Input Pin), Pin #12

The Slave Select (SS) input pin is shared with the ADC5 input. In order to configure this pin as a digital input the bit must be cleared, e.g., CLR P1.5.

This line is active low. Data is only received or transmitted in slave mode when the SS pin is low, allowing the ADuC812 to be used in single master, multislave SPI configurations. If CPHA = 1 then the SS input may be permanently pulled low. With CPHA = 0 then the SS input must be driven low before the first bit in a byte wide transmission or reception and return high again after the last bit in that byte wide transmission or reception. In SPI Slave Mode, the logic level on the external SS pin (Pin #13), can be read via the SPR0 bit in the SPICON SFR.

The following SFR registers are used to control the SPI interface.

SPICON

SPI Control Register

SFR Address

 

F8H

Power-On Default Value

OOH

Bit Addressable

 

Yes

ISPI

WCOL

SPE

SPIM

CPOL

CPHA

SPR1

SPR0

 

 

Table XI. SPICON SFR Bit Designations

 

 

 

Bit

Name

Description

 

 

 

7

ISPI

SPI Interrupt Bit.

 

 

Set by MicroConverter at the end of each SPI transfer.

 

 

Cleared directly by user code or indirectly by reading the SPIDAT SFR

6

WCOL

Write Collision Error Bit.

 

 

Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress.

 

 

Cleared by user code.

5

SPE

SPI Interface Enable Bit.

 

 

Set by user to enable the SPI interface.

 

 

Cleared by user to enable the I2C interface.

4

SPIM

SPI Master/Slave Mode Select Bit.

 

 

Set by user to enable Master Mode operation (SCLOCK is an output).

 

 

Cleared by user to enable Slave Mode operation (SCLOCK is an input).

3

CPOL

Clock Polarity Select Bit.

 

 

Set by user if SCLOCK idles high.

 

 

Cleared by user if SCLOCK idles low.

2

CPHA

Clock Phase Select Bit.

 

 

Set by user if leading SCLOCK edge is to transmit data.

 

 

Cleared by user if trailing SCLOCK edge is to transmit data.

 

 

 

–26–

REV. B

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional Equivalent Source and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters EXF2 C8HTF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK ET2 A8HEadc ET1Source Priority Description Source Vector AddressExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack
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