Analog Devices ADuC812 manual Other Hardware Considerations, In-Circuit Serial Download Access

Page 44

ADuC812

 

 

 

 

 

 

 

DOWNLOAD/DEBUG

 

 

 

 

 

 

 

 

 

 

ENABLE JUMPER

 

 

 

 

 

 

 

 

 

 

(NORMALLY OPEN)

 

 

 

 

 

 

 

DVDD

1k

 

DV

DD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1k

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2-PIN HEADER FOR

 

 

 

 

 

 

 

 

 

 

 

 

EMULATION ACCESS

 

52

51

50

49 48

 

47 46

45 44 43

42 41

40

 

 

(NORMALLY OPEN)

 

51

 

 

DV

 

DGND

 

PSEN

EA

 

 

 

ANALOG INPUT

ADC0

 

DD

 

 

 

 

39

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

38

 

 

 

 

 

 

 

 

 

 

 

37

 

 

AVDD

 

 

 

 

 

 

 

 

36

DVDD

 

AVDD

 

 

 

 

 

DGND 35

 

 

AGND

 

 

 

ADuC812

DVDD 34

 

VREF OUTPUT

CREF

 

 

 

 

 

XTAL2 33

11.0592MHz

VREF

 

 

 

 

 

XTAL1 32

 

 

 

 

 

 

 

 

DAC0

 

 

 

 

 

 

 

31

 

 

DAC1

 

 

 

 

 

 

 

30

 

DAC OUTPUT

ADC7

RESET

RxD

TxD

 

DV

DGND

 

 

29

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DD

 

 

 

28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

27

 

DVDD

ADM810

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

NOT CONNECTED IN THIS EXAMPLE

VCC

RST

 

 

 

DVDD

 

 

 

 

 

 

 

 

 

 

GND

 

 

 

ADM202

DVDD

9-PIN D-SUB

C1+

VCC

 

FEMALE

V+

GND

 

1

C1–

T1OUT

 

2

C2+

R1IN

 

3

C2–

R1OUT

 

4

V–

T1IN

 

5

T2OUT

T2IN

 

6

R2IN

R2OUT

 

7

 

 

 

8

 

 

 

9

Figure 46. Typical System Configuration

OTHER HARDWARE CONSIDERATIONS

To facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to download, debug, and emulation modes.

In-Circuit Serial Download Access

Nearly all ADuC812 designs will want to take advantage of the in-circuit reprogrammability of the chip. This is accomplished by a connection to the ADuC812’s UART, which requires an external RS-232 chip for level translation if downloading code from a PC. Basic configuration of an RS-232 connection is illustrated in Figure 46 with a simple ADM202-based circuit. If users would rather not design an RS-232 chip onto a board, refer to the applica- tion note “uC006–A 4-Wire UART-to-PC Interface”* for a simple (and zero-cost-per-board) method of gaining in-circuit serial download access to the ADuC812.

In addition to the basic UART connections, users will also need a way to trigger the chip into download mode. This is accom- plished via a 1 kΩ pull-down resistor that can be jumpered onto

*Application Note uC006 is available at www.analog.com/microconverter

the PSEN pin, as shown in Figure 46. To get the ADuC812 into download mode, simply connect this jumper and power- cycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program serially. With the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or RESET is toggled.

Note that PSEN is normally an output (as described in the External Memory Interface section) and it is sampled as an input only on the falling edge of RESET (i.e., at power-up or upon an external manual reset). Note also that if any external circuitry unintentionally pulls PSEN low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. To pre- vent this, ensure that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself.

Embedded Serial Port Debugger

From a hardware perspective, entry to serial port debug mode is identical to the serial download entry sequence described above. In fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways.

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REV. B

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812ADC Channel Specifications DC ACCURACY3 Calibrated Endpoint ERRORS5Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11DAC AC Characteristics FLASH/EE Memory Performance CHARACTERISTICS12Watchdog Timer Characteristics Power Supply Monitor CharacteristicsPower REQUIREMENTS14, 15 Digital OutputsIsource = 80 ∝A Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function ADC Specifications DAC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Circuit Information General OverviewADC Transfer Function Typical OperationEFH AQ1AQ0 #ADC Clks ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode Where the ADC Results are to be written. This is done by External memory must be preconfigured. This consistsDMAP. Dmal must be written to first, followed by Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence Econ B9HEadrl C6HCommand Byte Command Mode FDH ModeRNG1 RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 C0H PRE2PRE1 PRE0 PRE2 WDR1DFH DCHCMP PsmiF8H OOHIspi WcolSPR1 SPR0SPR1 SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF1 TR1TF0 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters C8H TF2EXF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM0 SM1SM0 SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK A8H EadcET2 ET1Source Priority Description Source Vector AddressExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator Down to 1.2 V or less. The timing diagram of illus ADuC812-based system as well as during its normal power-onLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsNormal Mode Idle ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations Quickstart Development System ADSIM-Windows SimulatorXTAL1 Period 83.33 62.5 1000 XTAL1 Width LowXTAL1 Width High XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Output Data Setup to Clock 700 10t CK Input Data Setup to Clock 300 2t CK +Serial Port Clock Cycle Time 12t CK Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Entire Data Sheet has been revised Outline DimensionsLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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