Analog Devices ADuC812 manual ADC Circuit Information, General Overview, ADC Transfer Function

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ADuC812

ADC CIRCUIT INFORMATION

General Overview

The ADC conversion block incorporates a fast, 8-channel, 12-bit, single supply A/D converter. This block provides the user with multichannel mux, track/hold, on-chip reference, calibration features and A/D converter. All components in this block are easily configured via a 3-register SFR interface.

The A/D converter consists of a conventional successive- approximation converter based around a capacitor DAC. The converter accepts an analog input range of 0 to +VREF. A high precision, low drift and factory calibrated 2.5 V reference is provided on-chip. The internal reference may be overdriven via the external VREF pin. This external reference can be in the range 2.3 V to AVDD.

Single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to the an external pin. Timer 2 can also be configured to generate a repeti- tive trigger for ADC conversions. The ADC may be configured to operate in a DMA Mode whereby the ADC block continu- ously converts and captures samples to an external RAM space without any interaction from the MCU core. This automatic capture facility can extend through a 16 MByte external Data Memory space.

The ADuC812 is shipped with factory programmed calibration coefficients which are automatically downloaded to the ADC on power-up ensuring optimum ADC performance. The ADC core contains internal Offset and Gain calibration registers. A software calibration routine is provided to allow the user to overwrite the factory programmed calibration coefficients if required, thus minimizing the impact of endpoint errors in the user’s target system.

Avoltage output from an On-Chip bandgap reference propor- tional to absolute temperature can also be routed through the front end ADC multiplexor (effectively a 9th ADC channel input) facilitating a temperature sensor implementation.

ADC Transfer Function

The analog input range for the ADC is 0 V to VREF. For this range, the designed code transitions occur midway between

successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, 5/2 LSBs . . . FS –3/2 LSBs). The output coding is straight binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when VREF = 2.5 V. The ideal input/output transfer characteristic for the 0 to VREF range is shown in Figure 5.

OUTPUT

 

 

CODE

 

 

111...111

 

 

111...110

 

 

111...101

 

 

111...100

FS

 

1LSB =

 

 

4096

 

000...011

 

 

000...010

 

 

000...001

 

 

000...000

 

 

0V 1LSB

VOLTAGE INPUT

+FS

 

–1LSB

 

 

Figure 5. ADC Transfer Function

Typical Operation

Once configured via the ADCCON 1-3 SFRs (shown on the following page) the ADC will convert the analog input and provide an ADC 12-bit result word in the ADCDATAH/L SFRs. The top 4 bits of the ADCDATAH SFR will be written with the channel selection bits so as to identify the channel result. The format of the ADC 12 bit result word is shown in Figure 6.

ADCDATAH SFR

CH–ID

HIGH 4 BITS OF

TOP 4 BITS

ADC RESULT WORD

ADCDATAL SFR

LOW 8 BITS OF THE

ADC RESULT WORD

Figure 6. ADC Result Format

–12–

REV. B

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812ADC Channel Specifications DC ACCURACY3 Calibrated Endpoint ERRORS5Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11DAC AC Characteristics FLASH/EE Memory Performance CHARACTERISTICS12Watchdog Timer Characteristics Power Supply Monitor CharacteristicsPower REQUIREMENTS14, 15 Digital OutputsIsource = 80 ∝A Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function ADC Specifications DAC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Circuit Information General OverviewADC Transfer Function Typical OperationEFH AQ1AQ0 #ADC Clks ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Where the ADC Results are to be written. This is done by External memory must be preconfigured. This consistsDMAP. Dmal must be written to first, followed by Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory Econ B9HEadrl C6HCommand Byte Command Mode FDH ModeRNG1 RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 C0H PRE2PRE1 PRE0 PRE2 WDR1DFH DCHCMP PsmiF8H OOHIspi WcolSPR1 SPR0SPR1 SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF1 TR1TF0 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter C8H TF2EXF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM0 SM1SM0 SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L A8H EadcET2 ET1Source Priority Description Source Vector AddressADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Down to 1.2 V or less. The timing diagram of illus ADuC812-based system as well as during its normal power-onLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsNormal Mode Idle ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Period 83.33 62.5 1000 XTAL1 Width LowXTAL1 Width High XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Output Data Setup to Clock 700 10t CK Input Data Setup to Clock 300 2t CK +Serial Port Clock Cycle Time 12t CK Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Entire Data Sheet has been revised Outline DimensionsLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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