Analog Devices ADuC812 manual Fdh, Mode, RNG1, RNG0, CLR1, CLR0, Sync, PD0

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ADuC812

USER INTERFACE TO OTHER ON-CHIP ADuC812

PERIPHERALS

The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given.

DAC

The ADuC812 incorporates two 12-bit, voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to VREF (the internal bandgap 2.5 V reference) and 0 V to AVDD.

Each can operate in 12-bit or 8-bit mode. Both DACs share a control register, DACCON, and four data registers, DAC1H/L, DAC0H/L. It should be noted that in 12-bit asynchronous mode, the DAC voltage output will be updated as soon as the DACL data SFR has been written; therefore, the DAC data registers should be updated as DACH first, followed by DACL.

DACCON

DAC Control Register

SFR Address

FDH

Power-On Default Value

04H

Bit Addressable

No

MODE

RNG1

RNG0

CLR1

CLR0

SYNC

PD1

PD0

 

 

 

Table VIII. DACCON SFR Bit Designations

 

 

 

 

 

Bit

 

Name

Description

 

 

 

 

 

7

 

MODE

The DAC MODE bit sets the overriding operating mode for both DACs.

 

 

 

Set to “1” = 8-Bit Mode (Write 8 Bits to DACxL SFR).

 

 

 

Set to “0”= 12-Bit Mode.

 

6

 

RNG1

DAC1 Range Select Bit.

 

 

 

 

Set to “1” = DAC1 Range 0–VDD.

 

 

 

 

Set to “0” = DAC1 Range 0–VREF.

 

5

 

RNG0

DAC0 Range Select Bit.

 

 

 

 

Set to “1” = DAC0 Range 0–VDD.

 

 

 

 

Set to “0” = DAC0 Range 0–VREF.

 

4

 

CLR1

DAC1 Clear Bit.

 

 

 

 

Set to “0” = DAC1 Output Forced to 0 V.

 

 

 

Set to “1” = DAC1 Output Normal.

 

3

 

CLR0

DAC0 Clear Bit.

 

 

 

 

Set to “0” = DAC1 Output Forced to 0 V.

 

 

 

Set to “1” = DAC1 Output Normal.

 

2

 

SYNC

DAC0/1 Update Synchronization Bit.

 

 

 

When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can

 

 

 

simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both

 

 

 

DACs will then update simultaneously when the SYNC bit is set to “1.”

1

 

PD1

DAC1 Power-Down Bit.

 

 

 

 

Set to “1” = Power-On DAC1.

 

 

 

 

Set to “0” = Power-Off DAC1.

 

0

 

PD0

DAC0 Power-Down Bit.

 

 

 

 

Set to “1” = Power-On DAC0.

 

 

 

 

Set to “0” = Power-Off DAC0.

 

 

 

 

 

DACxH/L

DAC Data Registers

 

Function

 

DAC Data Registers, written by user to update the DAC output.

SFR Address

DAC0L (DAC0 Data Low Byte) –>F9H; DAC1L (DAC1 Data Low Byte)->FBH

 

 

 

DAC0H (DAC0 Data High Byte) –>FAH; DAC1H(DAC1 Data High Byte)->FCH

Power-On Default Value

00H

–>All four Registers

Bit Addressable

No

–>All four Registers

The 12-bit DAC data should be written into DACxH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH contains the upper four bits.

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter TF2 C8HEXF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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