Analog Devices ADuC812 manual SFR area, Byte Program Sequence, Nonvolatile Flash Memory

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ADuC812

the gain calibration coefficient is divided into ADCGAINH (6 bits) and ADCGAINL (8 bits).The offset calibration coefficient compen- sates for dc offset errors in both the ADC and the input signal.

Increasing the offset coefficient compensates for positive offset, and effectively pushes the ADC Transfer Function DOWN. Decreasing the offset coefficient compensates for negative offset, and effectively pushes the ADC Transfer Function UP. The maximum offset that can be compensated is typically ± 5% of VREF, which equates to typically ± 125 mV with a 2.5 V reference.

Similarly, the gain calibration coefficient compensates for dc gain errors in both the ADC and the input signal.

Increasing the gain coefficient compensates for a smaller analog input signal range and scales the ADC Transfer Function UP, effectively increasing the slope of the transfer function. Decreas- ing the gain coefficient, compensates for a larger analog input signal range and scales the ADC Transfer Function DOWN, effectively decreasing the slope of the transfer function. The maximum analog input signal range for which the gain coeffi- cient can compensate is 1.025 ⋅ VREF and the minimum input range is 0.975 ⋅ VREF which equates to typically ± 2.5% of the reference voltage.

Calibration

Each ADuC812 is calibrated in the factory prior to shipping and the offset and gain calibration coefficients are stored in a hidden area of FLASH/EE memory. Each time the ADuC812 powers up, an internal power-on configuration routine, copies these coefficients into the offset and gain calibration registers in

the SFR area.

The MicroConverter ADC accuracy may vary from system to system due to board layout, grounding, clock speed, etc. To get the best ADC accuracy in your system, you should perform the software calibration routine described in the technical note uC005 available from the MicroConverter home page (www.analog.com/microconverter).

NONVOLATILE FLASH MEMORY

Flash Memory Overview

The ADuC812 incorporates Flash memory technology on-chip to provide the user with a nonvolatile, in-circuit reprogram- mable, code and data memory space.

Flash/EE memory is a relatively recent type of nonvolatile memory technology and is based on a single transistor cell architecture.

This technology is basically an outgrowth of EPROM technol- ogy and was developed through the late 1980s. Flash/EE memory takes the flexible in-circuit reprogrammable features of EEPROM and combines them with the space efficient/density features of EPROM (see Figure 14).

Because Flash/EE technology is based on a single transistor cell architecture, a Flash memory array, like EPROM, can be imple- mented to achieve the space efficiencies or memory densities required by a given design.

Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased; the erase being performed in page blocks. Thus, Flash memory is often and more correctly referred to as Flash/EE memory.

Overall, Flash/EE memory represents a step closer towards the ideal memory device that includes nonvolatility, in-circuit programmability, high density and low cost. Incorporated in the ADuC812, Flash/EE memory technology allows the user to

EPROM

EEPROM

TECHNOLOGY

TECHNOLOGY

SPACE EFFICIENT/

IN-CIRCUIT

DENSITY

REPROGRAMMABLE

FLASH/EE MEMORY

TECHNOLOGY

Figure 14. Flash Memory Development

update program code space in-circuit without the need to replace one-time programmable (OTP) devices at remote operating nodes.

Flash/EE Memory and the ADuC812

The ADuC812 provides two arrays of Flash/EE memory for user applications. 8K bytes of Flash/EE Program space are provided on-chip to facilitate code execution without any external discrete ROM device requirements. The program memory can be programmed using conventional third party memory programmers. This array can also be programmed in-circuit, using the serial download mode provided.

A 640-Byte Flash/EE Data Memory space is also provided on-chip. This may be used by the user as a general purpose nonvolatile scratchpad area. User access to this area is via a group of six SFRs.

ADuC812 Flash/EE Memory Reliability

The Flash/EE Program and Data Memory arrays on the ADuC812 are fully qualified for two key Flash/EE memory characteristics, namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention.

Endurance quantifies the ability of the Flash/EE memory to be cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as:

a. Initial Page Erase Sequence

 

b. Read/Verify Sequence

A single Flash/EE

c. Byte Program Sequence

Memory

d. Second Read/Verify Sequence

Endurance Cycle

In reliability qualification, every byte in both the program and data Flash/EE memory is cycled from 00 hex to FFhex until a first fail is recorded signifying the endurance limit of the on-chip Flash/EE memory.

As indicated in the specification pages of this data sheet, the ADuC812 Flash/EE Memory Endurance qualification has been carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C, +25°C, and +85°C. The results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles, with an endurance figure of 50,000 cycles being typical of operation at 25°C.

Retention quantifies the ability of the Flash/EE memory to retain its programmed data over time. Again, the ADuC812 has been qualified in accordance with the formal JEDEC Retention Life- time Specification (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed.

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter EXF2 C8HTF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET2 A8HEadc ET1Source Priority Description Source Vector AddressADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack
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