Analog Devices ADuC812 manual ARCHITECTURE, Main Features, Memory Organization

Page 9

ADuC812

ARCHITECTURE, MAIN FEATURES

The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- perfor- mance 8-bit (8052-Compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory control- ling a multichannel (8-input channels), 12-bit ADC.

The chip incorporates all secondary functions to fully support the programmable data acquisition core. These secondary functions include User Flash Memory, Watchdog Timer (WDT), Power Supply Monitor (PSM) and various industry- standard parallel and serial interfaces.

PROGRAM MEMORY SPACE

READ ONLY

FFFFH

BANKS

SELECTED

VIA

BITS IN PSW

11

10

01

00

7FH

2FH

20H

1FH

18H

17H

10H

0FH

08H

07H

00H

BIT-ADDRESSABLE SPACE (BIT ADDRESSES 0FH–7FH)

4 BANKS OF 8 REGISTERS

R0–R7

RESET VALUE OF STACK POINTER

EXTERNAL

PROGRAM

MEMORY

SPACE

2000H

 

EA = 1

1FFFH

EA = 0

INTERNAL

EXTERNAL

8K BYTE

PROGRAM

FLASH/EE

MEMORY

PROGRAM

SPACE

MEMORY

0000H

 

DATA MEMORY SPACE

READ/WRITE

Figure 2. Lower 128 Bytes of Internal RAM

MEMORY ORGANIZATION

As with all 8052-compatible devices, the ADuC812 has separate address spaces for Program and Data memory as shown in Fig- ure 1. Also as shown in Figure 1, an additional 640 Bytes of User Data Flash EEPROM are available to the user. The User Data Flash Memory area is accessed indirectly via a group of control registers mapped in the Special Function Register (SFR) area in the Data Memory Space.

The SFR space is mapped in the upper 128 bytes of internal data memory space. The SFR area is accessed by direct addressing only and provides an interface between the CPU and all on-chip peripherals. A block diagram showing the programming model of the ADuC812 via the SFR area is shown in Figure 3.

9FH

(PAGE 159)

640BYTES

FLASH/EE DATA

MEMORY

ACCESSED INDIRECTLY VIA SFR

CONTROL REGISTERS

00H

(PAGE 0)

 

 

 

 

INTERNAL

 

 

 

 

DATA MEMORY

 

 

 

 

SPACE

 

 

 

 

 

 

 

 

FFH

 

 

SPECIAL

 

ACCESSIBLE

 

FUNCTION

 

 

 

 

 

BY

REGISTERS

UPPER

INDIRECT

ACCESSIBLE

128

ADDRESSING

 

BY DIRECT

 

 

ONLY

ADDRESSING

 

80H

 

 

ONLY

 

7FH

ACCESSIBLE

 

 

LOWER

BY

 

 

DIRECT

 

 

128

 

 

AND

 

 

 

 

INDIRECT

 

 

 

 

ADDRESSING

 

 

FFFFFFH

EXTERNAL

DATA

MEMORY

SPACE

FFH(24-BIT ADDRESS

SPACE)

80H

8K BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE PROGRAM

MEMORY

 

 

 

 

 

128-BYTE

 

 

 

 

 

 

 

 

 

 

8051

 

 

 

SPECIAL

 

 

 

FUNCTION

COMPATIBLE

 

 

 

 

 

 

REGISTER

CORE

 

 

 

 

 

 

AREA

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

640-BYTE

ELECTRICALLY

REPROGRAMMABLE

NONVOLATILE

FLASH/EE DATA

MEMORY

AUTO-CALIBRATING

8-CHANNEL

HIGH SPEED

12-BIT ADC

OTHER ON-CHIP

PERIPHERALS TEMPERATURE SENSOR

2 12-BIT DACs

SERIAL I/O

PARALLEL I/O

WDT

PSM

00H

000000H

Figure 3. Programming Model

Figure 1. Program and Data Memory Maps

The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits) above the register banks form a block of bit addressable memory space at bit addresses 00H through 7FH.

REV. B

–9–

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Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter TF2 C8HEXF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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