Analog Devices ADuC812 manual Grounding and Board Layout Recommendations, System Grounding Schemes

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ADuC812

Grounding and Board Layout Recommendations

As with all high resolution data converters, special attention must be paid to grounding and PC board layout of ADuC812-based designs in order to achieve optimum performance from the ADCs and DAC.

Although the ADuC812 has separate pins for analog and digital ground (AGND and DGND), the user must not tie these to two separate ground planes unless the two ground planes are con- nected together very close to the ADuC812, as illustrated in the simplified example of Figure 45a. In systems where digital and analog ground planes are connected together somewhere else (at the system’s power supply for example), they cannot be con- nected again near the ADuC812 since a ground loop would result. In these cases, tie the ADuC812’s AGND and DGND pins all to the analog ground plane, as illustrated in Figure 45b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADuC812 can then be placed between the digital and analog sections, as illustrated in Figure 45c.

In all of these scenarios, and in more complicated real-life appli- cations, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 45b with DVDD since that would force return currents from DVDD to flow through AGND. Also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in Figure 45c. Whenever possible, avoid large discontinuities in the ground plane(s) (such as are formed by a long trace on the same layer), since they force return signals to travel a longer path. And of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground.

If the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADuC812’s digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADuC812 input pins. A value of 100 Ω or 200 Ω is usually sufficient to prevent high-speed signals from coupling capacitively into the ADuC812 and affecting the accuracy of ADC conversions.

A

PLACE ANALOG

PLACE DIGITAL

COMPONENTS HERE

COMPONENTS HERE

AGND

DGND

B

PLACE ANALOG

PLACE DIGITAL

COMPONENTS

COMPONENTS

HERE

HERE

AGND

DGND

C

PLACE ANALOG

PLACE DIGITAL

COMPONENTS

COMPONENTS

HERE

HERE

GND

Figure 45. System Grounding Schemes

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed byByte Program Sequence SFR areaNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2Rclk or Tclk CAP2 TR2 ModeOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B
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