Analog Devices ADuC812 manual Data Output Setup before Sclock Edge 150

Page 53

ADuC812

Parameter		Min	Typ	Max	Unit	Figure

SPI MASTER MODE TIMING (CPHA = 0)
tSL	SCLOCK Low Pulsewidth		330		ns	58
tSH	SCLOCK High Pulsewidth		330		ns	58
tDAV	Data Output Valid after SCLOCK Edge			50	ns	58
tDOSU	Data Output Setup before SCLOCK Edge			150	ns	58
tDSU	Data Input Setup Time before SCLOCK Edge	100			ns	58
tDHD	Data Input Hold Time after SCLOCK Edge	100			ns	58
tDF	Data Output Fall Time		10	25	ns	58
tDR	Data Output Rise Time		10	25	ns	58
tSR	SCLOCK Rise Time		10	25	ns	58
tSF	SCLOCK Fall Time		10	25	ns	58

SCLOCK (CPOL=0)

SCLOCK (CPOL=1)

MOSI

MISO

tSH

tDOSU

MSB

MSB IN

tDSU tDHD

tSL

tSRtSF

tDAV

tDF tDR

BIT 6 – 1	LSB
BIT 6 – 1	LSB IN

Figure 57. SPI Master Mode Timing (CPHA = 0)

REV. B

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Image 53

Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters TF2 C8HEXF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack

ADuC812

Parameter

SPI MASTER MODE TIMING (CPHA = 0)

Data Output Setup before SCLOCK Edge

150

SCLOCK Fall Time

Figure 57. SPI Master Mode Timing (CPHA = 0)

REV. B