Analog Devices ADuC812 manual SPR1 SPR0, F7H

Page 27

ADuC812

Table XII. SPICON SFR Bit Designations (continued)

Bit

Name

Description

 

 

 

 

1

SPR1

SPI Bit-Rate Select Bits.

0

SPR0

These bits select the SCLOCK rate (bit-rate) in Master Mode as follows:

 

 

SPR1

SPR0

Selected Bit Rate

 

 

0

0

fOSC/4

 

 

0

1

fOSC/8

 

 

1

0

fOSC/32

 

 

1

1

fosc/64

 

 

In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin #12)

 

 

can be read via the SPR0 bit.

 

 

 

 

 

NOTE

The CPOL and CPHA bits should both contain the same values for master and slave devices.

SPIDAT

SPI Data Register

Function

The SPIDAT SFR is written by the

 

user to transmit data over the SPI

 

interface or read by user code to

 

read data just received by the SPI

 

interface.

SFR Address

F7H

Power-On Default Value

00H

Bit Addressable

No

Using the SPI Interface

Depending on the configuration of the bits in the SPICON SFR shown in Table XII, the ADuC812 SPI interface will transmit or receive data in a number of possible modes. Figure 26 shows all possible ADuC812 SPI configurations and the timing rela- tionships and synchronization between the signals involved. Also shown in this figure is the SPI interrupt bit (ISPI) and how it is triggered at the end of each byte-wide communication.

SCLOCK (CPOL = 1)

SCLOCK (CPOL = 0)

SS

SAMPLE INPUT

 

=1)

? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB

DATA OUTPUT

(CPHA

 

ISPI FLAG

 

SAMPLE INPUT

 

=0)

MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ?

DATA OUTPUT

(CPHA

 

ISPI FLAG

Figure 25. SPI Timing, All Modes

SPI Interface—Master Mode

In master mode, the SCLOCK pin is always an output and gener- ates a burst of eight clocks whenever user code writes to the SPIDAT register. The SCLOCK bit rate is determined by SPR0 and SPR1 in SPICON. It should also be noted that the

SSpin is not used in master mode. If the ADuC812 needs to assert the SS pin on an external slave device, a Port digital output pin should be used.

In master mode a byte transmission or reception is initiated by a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period a data bit is also sampled via MISO. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT.

SPI Interface—Slave Mode

In slave mode the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication.

Transmission is also initiated by a write to SPIDAT. In slave mode, a data bit is transmitted via MISO and a data bit is received via MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT only when the transmission/reception of a byte has been completed.

The end of transmission occurs after the eighth clock has been received if CPHA = 1, or when SS returns high if CPHA = 0.

REV. B

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Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed bySFR area Byte Program SequenceNonvolatile Flash Memory C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter Rclk C8HTF2 EXF2CAP2 TR2 Mode Rclk or TclkOFF SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B
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