Analog Devices ADuC812 manual Smod, Clk, RCAP2H RCAP2L

Page 37

ADuC812

Timer 1 Generated Baud Rates

When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows:

Modes 1 and 3 Baud Rate =

(2SMOD/32) ⋅ (Timer 1 Overflow Rate)

The Timer 1 interrupt should be disabled in this application. The Timer itself can be configured for either timer or counter opera- tion, and in any of its three running modes. In the most typical application, it is configured for timer operation, in the Autoreload mode (high nibble of TMOD = 0010 Binary). In that case, the baud rate is given by the formula:

Modes 1 and 3 Baud Rate = (2SMOD/32) ⋅ (Core Clock/(12 ⋅ [256-TH1]))

Table XXI shows some commonly-used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz and 12 MHz. Generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications.

Table XXI. Commonly-Used Baud Rates, Timer 1

Ideal

Core

SMOD

TH1-Reload

Actual

%

Baud

CLK

Value

Value

Baud

Error

 

 

 

 

 

 

9600

12

1

–7 (F9h)

8929

7

19200

11.0592

1

–3 (FDh)

19200

0

9600

11.0592

0

–3 (FDh)

9600

0

2400

11.0592

0

–12(F4h)

2400

0

 

 

 

 

 

 

Timer 2 Generated Baud Rates

Baud rates can also be generated using Timer 2. Using Timer 2 is similar to using Timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. Because Timer 2 has a 16-bit Autoreload mode a wider range of baud rates is possible using Timer 2.

Modes 1 and 3 Baud Rate = (1/16) ⋅ (Timer 2 Overflow Rate)

Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. Hence, it increments six times faster than Timer 1, and therefore baud rates six times faster are possible. Because Timer 2 has 16-bit autoreload capability, very low baud rates are still possible.

Timer 2 is selected as the baud rate generator by setting the TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode as shown in Figure 34.

In this case, the baud rate is given by the formula:

Modes 1 and 3 Baud Rate -

(Core Clk)/(32 ⋅ [65536 – (RCAP2H, RCAP2L)])

Table XXII shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz and 12 MHz.

Table XXII. Commonly Used Baud Rates, Timer 2

Ideal

Core

RCAP2H

RCAP2L

Actual

%

Baud

CLK

Value

Value

Baud

Error

 

 

 

 

 

 

 

19200

12

–1 (FFh)

–20

(ECh)

19661

2.4

9600

12

–1 (FFh)

–41

(D7h)

9591

0.1

2400

12

–1 (FFh)

–164 (5Ch)

2398

0.1

1200

12

–2 (FEh)

–72

(B8h)

1199

0.1

19200

11.0592

–1 (FFh)

–18

(EEh)

19200

0

9600

11.0592

–1 (FFh)

–36

(DCh)

9600

0

2400

11.0592

–1 (FFh)

–144(70h)

2400

0

1200

11.0592

–2 (FFh)

–32

(E0h)

1200

0

 

 

 

 

 

 

 

NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12.

CORE

2

CONTROL

TIMER 1

OVERFLOW

2

 

0

1

SMOD

CLK

C/T2 = 0

T2

C/T2 = 1

 

PIN

 

 

TR2

NOTE: AVAILABILITY OF ADDITIONAL

EXTERNAL INTERRUPT

 

 

 

TIMER 2

 

TL2

TH2

OVERFLOW 1

0

(8-BITS)

(8-BITS)

 

 

 

 

1

0

 

 

RELOAD

 

RCAP2L

RCAP2H

 

 

RCLK

16

TCLK

16

RX CLOCK

TX CLOCK

T2EX

EXF

PIN

2

CONTROL

TRANSITION

DETECTOR

EXEN2

TIMER 2 INTERRUPT

Figure 34. Timer 2, UART Baud Rates

REV. B

–37–

Image 37
Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝APIN Configuration Temperature Package Model Range Description OptionOrdering Guide Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CCS3 CS2 CS1 CS0 CH# Location Name DescriptionBit Location Status Description Driving the A/D Converter Op Amp Model CharacteristicsTable VI. Some Single-Supply Op Amps ADC DMA Mode Configuring the ADCVoltage Reference Connections External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapByte Program Sequence SFR areaNonvolatile Flash Memory B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0Mode 3 Two 8-Bit Timer/Counters TIMER/COUNTER 0 and 1 Operating ModesMode 1 16-Bit Timer/Counter TF2 C8HEXF2 RclkRclk or Tclk CAP2 TR2 ModeOFF SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed CLK SmodRCAP2H RCAP2L Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionClock Oscillator ADuC812 Hardware Design ConsiderationsExternal Memory Interface ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsOther Hardware Considerations In-Circuit Serial Download AccessEmbedded Serial Port Debugger ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS to Sclock Edge SPI Slave Mode Timing Cpha =SS High after Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack