Analog Devices ADuC812 manual Digital Outputs, Isource = 80 ∝A, Isource = 20 ∝A

Page 5

 

 

 

 

ADuC812

 

ADuC812BS

 

 

Parameter

VDD = 5 V

VDD = 3 V

Unit

Test Conditions/Comments

DIGITAL OUTPUTS

 

 

 

 

Output High Voltage (VOH)

2.4

 

V min

VDD = 4.5 V to 5.5 V

 

 

 

 

ISOURCE = 80 ∝A

 

4.0

2.6

V typ

VDD = 2.7 V to 3.3 V

Output Low Voltage (VOL)

 

 

 

ISOURCE = 20 ∝A

 

 

 

 

ALE, PSEN, Ports 0 and 2

0.4

 

V max

ISINK = 1.6 mA

 

0.2

0.2

V typ

ISINK = 1.6 mA

Port 3

0.4

 

V max

ISINK = 8 mA

 

0.2

0.2

V typ

ISINK = 8 mA

Floating State Leakage Current

± 10

 

∝A max

 

 

± 5

± 5

∝A typ

 

Floating State Output Capacitance

10

10

pF typ

 

 

 

 

 

 

POWER REQUIREMENTS14, 15, 16

 

 

 

 

IDD Normal Mode17

43

 

mA max

MCLKIN = 16 MHz

 

32

16

mA typ

MCLKIN = 16 MHz

 

26

12

mA typ

MCLKIN = 12 MHz

 

8

3

mA typ

MCLKIN = 1 MHz

IDD Idle Mode

25

 

mA max

MCLKIN = 16 MHz

 

18

17

mA typ

MCLKIN = 16 MHz

 

15

6

mA typ

MCLKIN = 12 MHz

 

7

2

mA typ

MCLKIN = 1 MHz

IDD Power-Down Mode18

50

50

∝A max

 

 

5

5

∝A typ

 

 

 

 

 

 

NOTES

1Specifications apply after calibration.

2Temperature range –40°C to +85°C.

3Linearity is guaranteed during normal MicroConverter Core operation.

4Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity.

5Measured in production at VDD = 5 V after Software Calibration Routine at 25°C only.

6User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent.

7The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate.

8SNR calculation includes distortion and noise components.

9Specification is not production tested, but is supported by characterization data at initial product release.

10The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result.

11DAC linearity is calculated using:

reduced code range of 48 to 4095, 0 to VREF range reduced code range of 48 to 3995, 0 to VDD range DAC output load = 10 kΩ and 50 pF.

12Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance).

13Endurance Cycling is evaluated under the following conditions:

Mode

= Byte Programming, Page Erase Cycling

Cycle Pattern

= 00Hex to FFHex

Erase Time

= 20 ms

Program Time

= 100 ∝s

14IDD at other MCLKIN frequencies is typically given by:

Normal Mode (VDD = 5 V):

IDD = (1.6 nAs ⋅ MCLKIN) + 6 mA

Normal Mode (VDD = 3 V):

IDD = (0.8 nAs ⋅ MCLKIN) + 3 mA

Idle Mode (VDD = 5 V):

IDD = (0.75 nAs ⋅ MCLKIN) + 6 mA

Idle Mode (VDD = 3 V):

IDD = (0.25 nAs ⋅ MCLKIN) + 3 mA

Where MCLKIN is the oscillator frequency in MHz and resultant I DD values are in mA.

15IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation. 16IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles.

17Analog IDD = 2 mA (typ) in normal operation (internal VREF, ADC and DAC peripherals powered on).

18EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement.

Typical specifications are not production tested, but are supported by characterization data at initial product release.

Specifications subject to change without notice.

Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information.

REV. B

–5–

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Contents General Description Functional Block DiagramADuC812 Table of ContentsCalibrated Endpoint ERRORS5 ADC Channel Specifications DC ACCURACY3Temperature SENSOR10 DAC Channel Specifications DC ACCURACY11FLASH/EE Memory Performance CHARACTERISTICS12 DAC AC CharacteristicsWatchdog Timer Characteristics Power Supply Monitor CharacteristicsDigital Outputs Power REQUIREMENTS14, 15Isource = 80 ∝A Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function DAC Specifications ADC SpecificationsTerminology Thus for a 12-bit converter, this is 74 dBMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesGeneral Overview ADC Circuit InformationADC Transfer Function Typical OperationAQ1 EFHAQ0 #ADC Clks ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode External memory must be preconfigured. This consists Where the ADC Results are to be written. This is done byDMAP. Dmal must be written to first, followed by Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence B9H EconEadrl C6HCommand Byte Command Mode Mode FDHRNG1 RNG0Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 PRE2 C0HPRE1 PRE0 PRE2 WDR1DCH DFHCMP PsmiOOH F8HIspi WcolSPR0 SPR1SPR1 SPR0 F7H2C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR1 TF1TF0 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters TF2 C8HEXF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM1 SM0SM0 SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK Eadc A8HET2 ET1Source Vector Address Source Priority DescriptionExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator ADuC812-based system as well as during its normal power-on Down to 1.2 V or less. The timing diagram of illusLevel. The external POR circuit must be operational High it tracks the voltage on DVDD. These recommendationsIdle Mode Normal ModeVDD = 5 VDD = 3 Core NAs ⋅ Mclk +System Grounding Schemes Grounding and Board Layout RecommendationsEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Width Low XTAL1 Period 83.33 62.5 1000XTAL1 Width High XTAL1 Rise TimeExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Setup to Clock 300 2t CK + Output Data Setup to Clock 700 10t CKSerial Port Clock Cycle Time 12t CK Input Data Hold after ClockI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Outline Dimensions Entire Data Sheet has been revisedLocation Data Sheet changed from REV. a to REV. B Lead Plastic Quad Flatpack
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