Analog Devices ADuC812 A8H, Eadc, ET2, ET1, EX1, ET0, EX0, B8H, Psi, Padc, PT2, PT1, PX1, PT0

Page 38

ADuC812

INTERRUPT SYSTEM

The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs.

IE:	Interrupt Enable Register.
IP:	Interrupt Priority Register.
IE2:	Secondary Interrupt Enable Register.

IE:	Interrupt Enable Register
SFR Address	A8H
Power-On Default Value	00H
Bit Addressable	Yes

EA

EADC

ET2

ES

ET1

EX1

ET0

EX0

			Table XXIII. IE SFR Bit Designations

Bit		Name	Description

7		EA	Written by User to Enable “1” or Disable “0” All Interrupt Sources
6		EADC	Written by User to Enable “1” or Disable “0” ADC Interrupt
5		ET2	Written by User to Enable “1” or Disable “0” Timer 2 Interrupt
4		ES	Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt
3		ET1	Written by User to Enable “1” or Disable “0” Timer 1 Interrupt
2		EX1	Written by User to Enable “1” or Disable “0” External Interrupt 1
1		ET0	Written by User to Enable “1” or Disable “0” Timer 0 Interrupt
0		EX0	Written by User to Enable “1” or Disable “0” External Interrupt 0

IP:			Interrupt Priority Register
SFR Address			B8H
Power-On Default Value			00H
Bit Addressable			Yes

PSI

PADC

PT2

PS

PT1

PX1

PT0

PX0

		Table XXIV. IP SFR Bit Designations

Bit	Name	Description

7	PSI	Written by User to Select SPI/I2C Priority (“1” = High; “0” = Low)
6	PADC	Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low)
5	PT2	Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low)
4	PS	Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low)
3	PT1	Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low)
2	PX1	Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low)
1	PT0	Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low)
0	PX0	Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low)

–38–

REV. B

Image 38

Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters EXF2 C8HTF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK ET2 A8HEadc ET1Source Priority Description Source Vector AddressExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack