Analog Devices ADuC812 manual Source and Sink Current Capability with Vref = VDD = 3

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		3
	– V	2
	VOLTAGE	2
	VOLTAGE
	OUTPUT	1
		1

0

0

5

10

15

SOURCE/SINK CURRENT – mA

Figure 21. Source and Sink Current Capability with VREF = VDD = 3 V

To drive significant loads with the DAC outputs, external buff- ering may be required, as illustrated in Figure 22.

ADuC812

the DAC outputs will remain at ground potential whenever the DAC is disabled. However, each DAC output will still spike briefly when you first apply power to the chip, and again when each DAC is first enabled in software. Typical scope shots of these spikes are given in Figure 23 and Figure 24 respectively.

200	s/DIV
	AVDD – 2V/DIV
	DAC OUT – 500mv/DIV

Figure 23. DAC Output Spike at Chip Power-Up

9	ADuC812

10

Figure 22. Buffering the DAC Outputs

The DAC output buffer also features a high-impedance disable function. In the chip’s default power-on state, both DACs are disabled, and their outputs are in a high-impedance state (or “three-state”) where they remain inactive until enabled in software. This means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each DAC output. Assuming this resistor is in place,

5 s/DIV, 1V/DIV

Figure 24. DAC Output Spike at DAC Enable

REV. B

–23–

Image 23

Contents General Description Functional Block DiagramADuC812 Table of ContentsDAC Channel Specifications DC ACCURACY11 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 Temperature SENSOR10Power Supply Monitor Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Watchdog Timer CharacteristicsIsource = 20 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 80 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function Thus for a 12-bit converter, this is 74 dB ADC SpecificationsDAC Specifications TerminologyMemory Organization ARCHITECTURE, Main FeaturesBit Name Description Special Function Registers Default Value SFR Address SFR NotesTypical Operation ADC Circuit InformationGeneral Overview ADC Transfer FunctionADCCON1.1 T2C EFHAQ1 AQ0 #ADC ClksBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode Dmah and then by Dmap Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists DMAP. Dmal must be written to first, followed byNonvolatile Flash Memory SFR areaByte Program Sequence C6H EconB9H EadrlCommand Byte Command Mode RNG0 FDHMode RNG1Resistor String DAC Functional Equivalent Using the D/A ConverterSource and Sink Current Capability with Vref = VDD = 3 WDR1 C0HPRE2 PRE1 PRE0 PRE2Psmi DFHDCH CMPWcol F8HOOH IspiF7H SPR1SPR0 SPR1 SPR02C Control Register I2CCONCompatible ON-CHIP Peripherals Pin Alternate FunctionT2CON TMOD, TconTR0 TF1TR1 TF0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters Rclk C8HTF2 EXF2OFF CAP2 TR2 ModeRclk or Tclk SM2 SM0SM1 SM0 SM1Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK ET1 A8HEadc ET2Source Vector Address Source Priority DescriptionExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator High it tracks the voltage on DVDD. These recommendations Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on Level. The external POR circuit must be operationalCore NAs ⋅ Mclk + Normal ModeIdle Mode VDD = 5 VDD = 3System Grounding Schemes Grounding and Board Layout RecommendationsEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations ADSIM-Windows Simulator Quickstart Development SystemXTAL1 Rise Time XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Width HighExternal Program Memory 12 MHz Variable Clock Parameter Min Max UnitExternal Data Memory Read Cycle External Data Memory Write Cycle Input Data Hold after Clock Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Serial Port Clock Cycle Time 12t CKI2C-COMPATIBLE Interface Timing Parameter Min Max UnitParameter Min Typ Max Unit SPI Master Mode Timing Cpha =Data Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Lead Plastic Quad Flatpack Entire Data Sheet has been revisedOutline Dimensions Location Data Sheet changed from REV. a to REV. B