Analog Devices ADuC812 manual Table of Contents

Page 2

ADuC812

TABLE OF CONTENTS

FEATURES

. 1

GENERAL DESCRIPTION

. 1

SPECIFICATIONS

. 3

ABSOLUTE MAXIMUM RATINGS

. 6

ORDERING GUIDE

. 6

PIN FUNCTION DISCRIPTIONS

. 7

TERMINOLOGY

. 8

ADC SPECIFICATIONS

. 8

Integral Nonlinearity

. 8

Differential Nonlinearity

. 8

Offset Error

. 8

Full-Scale Error

. 8

Signal to (Noise + Distortion) Ratio

. 8

Total Harmonic Distortion

. 8

DAC SPECIFICATIONS

. 8

Relative Accuracy

. 8

Voltage Output Settling Time

. 8

Digital-to-Analog Glitch Impulse

. 8

ARCHITECTURE, MAIN FEATURES

. 9

MEMORY ORGANIZATION

. 9

OVERVIEW OF MCU-RELATED SFRs

10

Accumulator SFR

10

B SFR

10

Stack Pointer SFR

10

Data Pointer

10

Program Status Word SFR

10

Power Control SFR

10

SPECIAL FUNCTION REGISTERS

11

ADC CIRCUIT INFORMATION

12

General Overview

12

ADC Transfer Function

12

Typical Operation

12

ADCCON1 – (ADC Control SFR #1)

13

ADCCON2 – (ADC Control SFR #2)

14

ADCCON3 – (ADC Control SFR #3)

14

Driving the A/D Converter

15

Voltage Reference Connections

16

Configuring the ADC

16

ADC DMA Mode

16

Micro Operation during ADC DMA Mode

17

The Offset and Gain Calibration Coefficients

17

Calibration

18

NONVOLATILE FLASH MEMORY

18

Flash Memory Overview

18

Flash/EE Memory and the ADuC812

18

ADuC812 Flash/EE Memory Reliability

18

Using the Flash/EE Program Memory

19

Using the Flash/EE Data Memory

19

ECON—Flash/EE Memory Control SFR

20

Flash/EE Memory Timing

20

Using the Flash/EE Memory Interface

20

Erase-All

20

Program a Byte

20

USER INTERFACE TO OTHER ON-CHIP

 

ADuC812 PERIPHERALS

21

Using the D/A Converter

22

WATCHDOG TIMER

24

POWER SUPPLY MONITOR

25

SERIAL PERIPHERAL INTERFACE

26

MISO (Master In, Slave Out Data I/O Pin), Pin #19

26

MOSI (Master Out, Slave In Pin), Pin #27

26

SCLOCK (Serial Clock I/O Pin), Pin #26

26

SS (Slave Select Input Pin), Pin #12

26

Using the SPI Interface

27

SPI Interface—Master Mode

27

SPI Interface—Slave Mode

27

I2C-COMPATIBLE INTERFACE

28

8051-COMPATIBLE ON-CHIP PERIPHERALS

29

Parallel I/O Ports 0–3

29

Timers/Counters

29

Timer/Counter 0 and 1 Data Registers

31

TH0 and TL0

31

TH1 and TL1

31

TIMER/COUNTER 0 AND 1 OPERATING MODES

32

Mode 0 (13-Bit Timer/Counter)

32

Mode 1 (16-Bit Timer/Counter)

32

Mode 2 (8-Bit Timer/Counter with Auto Reload)

32

Mode 3 (Two 8-Bit Timer/Counters)

32

Timer/Counter 2 Data Registers

33

TH2 and TL2

33

RCAP2H and RCAP2L

33

Timer /Counter Operation Modes

34

16-Bit Autoreload Mode

34

16-Bit Capture Mode

34

UART SERIAL INTERFACE

35

Mode 0: 8-Bit Shift Register Mode

36

Mode 1: 8-Bit UART, Variable Baud Rate

36

Mode 2: 9-Bit UART with Fixed Baud Rate

36

Mode 3: 9-Bit UART with Variable Baud Rate

36

UART Serial Port Baud Rate Generation

36

Timer 1 Generated Baud Rates

37

Timer 2 Generated Baud Rates

37

INTERRUPT SYSTEM

38

Interrupt Priority

39

Interrupt Vectors

39

ADuC812 HARDWARE DESIGN CONSIDERATIONS . . . . 40

Clock Oscillator

40

External Memory Interface

40

Power-On Reset Operation

41

Power Supplies

41

Power Consumption

42

Power-Saving Modes

42

Grounding and Board Layout Recommendations

43

OTHER HARDWARE CONSIDERATIONS

44

In-Circuit Serial Download Access

44

Embedded Serial Port Debugger

44

Single-Pin Emulation Mode

45

Enhanced-Hooks Emulation Mode

45

Typical System Configuration

45

QUICKSTART DEVELOPMENT SYSTEM

45

Download—In-Circuit Serial Downloader

45

DeBug—In-Circuit Debugger

45

ADSIM—Windows Simulator

45

TIMING SPECIFICATIONS

46

OUTLINE DIMENSIONS

56

Revision History

56

–2–

REV. B

Page 1 Page 3
Image 2
Page 1 Page 3
Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝AOrdering Guide Temperature Package Model Range Description OptionPIN Configuration Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CBit Location Status Description Location Name DescriptionCS3 CS2 CS1 CS0 CH# Table VI. Some Single-Supply Op Amps Op Amp Model CharacteristicsDriving the A/D Converter Voltage Reference Connections Configuring the ADCADC DMA Mode DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapNonvolatile Flash Memory SFR areaByte Program Sequence Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0Mode 1 16-Bit Timer/Counter TIMER/COUNTER 0 and 1 Operating ModesMode 3 Two 8-Bit Timer/Counters EXF2 C8HTF2 RclkOFF CAP2 TR2 ModeRclk or Tclk SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed RCAP2H RCAP2L SmodCLK ET2 A8HEadc ET1Source Priority Description Source Vector AddressExternal Memory Interface ADuC812 Hardware Design ConsiderationsClock Oscillator Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesEmbedded Serial Port Debugger In-Circuit Serial Download AccessOther Hardware Considerations Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SS High after Sclock Edge SPI Slave Mode Timing Cpha =SS to Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack
Top Page Image Contents