Analog Devices ADuC812 manual VDD = 5 VDD = 3, Core NAs ⋅ Mclk +, Normal Mode, Idle Mode, Adc

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ADuC812

As an alternative to providing two separate power supplies, the user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 44. With this configuration other analog cir- cuitry (such as op amps, voltage reference, etc.) can be powered from the AVDD supply line as well. Thne user will still want to include back-to-back Schottky diodes between AVDD and DVDD in order to protect from power-up and power-down transient conditions that could separate the two supply voltages momentarily.

DIGITAL SUPPLY

 

 

 

+

10 F

BEAD

1.6V

10 F

–

 

ADuC812

 

 

 

 

 

20

 

 

 

 

34

DVDD

AVDD

5

 

 

 

 

0.1 F

 

48

 

 

 

0.1

F

 

 

 

 

21

 

 

 

 

35

DGND

 

 

 

47

 

AGND 6

 

 

 

 

Figure 44. External Single-Supply Connections

Notice that in both Figure 43 and Figure 44, a large value (10 ∝F) reservoir capacitor sits on DVDD and a separate 10 ∝F capacitor sits on AVDD. Also, local small-value (0.1 ∝F) capacitors are located at each VDD pin of the chip. As per standard design prac- tice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each AVDD pin with trace lengths as short as possible. Connect the ground terminal of each of these capacitors directly to the underlying ground plane. Finally, it should also be noted that, at all times, the analog and digital ground pins on the ADuC812 must be referenced to the same system ground reference point.

Power Consumption

The currents consumed by the various sections of the ADuC812 are shown in Table XXVIII. The “CORE” values given represent the current drawn by DVDD, while the rest (“ADC,” “DAC,” “voltage ref”) are pulled by the AVDD pin and can be disabled in software when not in use. The other on-chip peripherals (watchdog timer, power supply monitor, etc.) consume negligible current and are therefore lumped in with the “CORE” operating current here. Of course, the user must add any currents sourced by the parallel and serial I/O pins, and that sourced by the DAC, in order to determine the total current needed at the ADuC812’s supply pins. Also, current drawn from the DVDD supply will increase by approximately 10 mA during Flash/EE erase and program cycles.

Table XXVIII. Typical IDD of Core and Peripherals

 

VDD = 5 V

VDD = 3 V

 

 

 

Core:

(1.6 nAs ⋅ MCLK) +

(0.8 nAs ⋅ MCLK) +

(Normal Mode)

 

6 mA

3 mA

Core:

(0.75 nAs ⋅ MCLK) +

(0.25 nAs ⋅ MCLK) +

(Idle Mode)

 

5 mA

3 mA

ADC:

1.3 mA

1.0 mA

DAC (Each):

250 ∝A

200 ∝A

Voltage Ref:

200 ∝A

150 ∝A

 

 

 

Since operating DVDD current is primarily a function of clock speed, the expressions for “CORE” supply current in Table XXVIII are given as functions of MCLK, the oscillator frequency. Plug in a value for MCLK in hertz to determine the current con- sumed by the core at that oscillator frequency. Since the ADC and DACs can be enabled or disabled in software, add only the currents from the peripherals you expect to use. The internal voltage reference is automatically enabled whenever either the ADC or at least one DAC is enabled. And again, do not forget to include current sourced by I/O pins, serial port pins, DAC outputs, etc., plus the additional current drawn during Flash/EE erase and program cycles.

A software switch allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. Below are brief descriptions of power-down and idle modes.

In idle mode, the oscillator continues to run, but is gated off to the core only. The on-chip peripherals continue to receive the clock, and remain functional. Port pins and DAC output pins retain their states in this mode. The chip will recover from idle mode upon receiving any enabled interrupt, or on receiving a hardware reset.

In full power-down mode, the on-chip oscillator stops, and all on-chip peripherals are shut down. Port pins retain their logic levels in this mode, but the DAC output goes to a high-impedance state (three-state). The chip will only recover from power-down mode upon receiving a hardware reset or when power is cycled. During full power-down mode, the ADuC812 consumes a total of approximately 5 ∝A.

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REV. B

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Contents Functional Block Diagram General DescriptionTable of Contents ADuC812Temperature SENSOR10 ADC Channel Specifications DC ACCURACY3Calibrated Endpoint ERRORS5 DAC Channel Specifications DC ACCURACY11Watchdog Timer Characteristics DAC AC CharacteristicsFLASH/EE Memory Performance CHARACTERISTICS12 Power Supply Monitor CharacteristicsIsource = 80 ∝A Power REQUIREMENTS14, 15Digital Outputs Isource = 20 ∝ATemperature Package Model Range Description Option PIN ConfigurationOrdering Guide Mnemonic Type Function Terminology ADC SpecificationsDAC Specifications Thus for a 12-bit converter, this is 74 dBARCHITECTURE, Main Features Memory OrganizationBit Name Description Default Value SFR Address SFR Notes Special Function RegistersADC Transfer Function ADC Circuit InformationGeneral Overview Typical OperationAQ0 #ADC Clks EFHAQ1 ADCCON1.1 T2CLocation Name Description CS3 CS2 CS1 CS0 CH#Bit Location Status Description Op Amp Model Characteristics Driving the A/D ConverterTable VI. Some Single-Supply Op Amps Configuring the ADC ADC DMA ModeVoltage Reference Connections DMAP. Dmal must be written to first, followed by Where the ADC Results are to be written. This is done byExternal memory must be preconfigured. This consists Dmah and then by DmapSFR area Byte Program SequenceNonvolatile Flash Memory Eadrl EconB9H C6HCommand Byte Command Mode RNG1 FDHMode RNG0Using the D/A Converter Resistor String DAC Functional EquivalentSource and Sink Current Capability with Vref = VDD = 3 PRE1 PRE0 PRE2 C0HPRE2 WDR1CMP DFHDCH PsmiIspi F8HOOH WcolSPR1 SPR0 SPR1SPR0 F7HI2CCON 2C Control RegisterPin Alternate Function Compatible ON-CHIP PeripheralsTMOD, Tcon T2CONTF0 TF1TR1 TR0TIMER/COUNTER 0 and 1 Operating Modes Mode 3 Two 8-Bit Timer/CountersMode 1 16-Bit Timer/Counter EXF2 C8HTF2 RclkCAP2 TR2 Mode Rclk or TclkOFF SM0 SM1 SM0SM1 SM2Baud rate in Mode 0 is fixed Smod CLKRCAP2H RCAP2L ET2 A8HEadc ET1Source Priority Description Source Vector AddressADuC812 Hardware Design Considerations Clock OscillatorExternal Memory Interface Level. The external POR circuit must be operational Down to 1.2 V or less. The timing diagram of illusADuC812-based system as well as during its normal power-on High it tracks the voltage on DVDD. These recommendationsVDD = 5 VDD = 3 Normal ModeIdle Mode Core NAs ⋅ Mclk +Grounding and Board Layout Recommendations System Grounding SchemesIn-Circuit Serial Download Access Other Hardware ConsiderationsEmbedded Serial Port Debugger Quickstart Development System ADSIM-Windows SimulatorXTAL1 Width High XTAL1 Period 83.33 62.5 1000XTAL1 Width Low XTAL1 Rise Time12 MHz Variable Clock Parameter Min Max Unit External Program MemoryExternal Data Memory Read Cycle External Data Memory Write Cycle Serial Port Clock Cycle Time 12t CK Output Data Setup to Clock 700 10t CKInput Data Setup to Clock 300 2t CK + Input Data Hold after ClockParameter Min Max Unit I2C-COMPATIBLE Interface TimingSPI Master Mode Timing Cpha = Parameter Min Typ Max UnitData Output Setup before Sclock Edge 150 SPI Slave Mode Timing Cpha = SS to Sclock EdgeSS High after Sclock Edge Data Output Valid after SS Edge Location Data Sheet changed from REV. a to REV. B Entire Data Sheet has been revisedOutline Dimensions Lead Plastic Quad Flatpack
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