Xilinx PLB PCI Full Bridge specifications Ipif Parameters Group

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PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

	Generic	Feature /	Parameter	Allowable Values	Default	VHDL
	Generic	Description	Name	Allowable Values	Value	Type
		Description	Name		Value	Type

		Include configuration	C_INCLUDE_	0 = Not included
	G61	functionality via IPIF	C_INCLUDE_	0 = Not included	1	integer
	G61	functionality via IPIF	PCI_CONFIG	1 = Included	1	integer
		transactions	PCI_CONFIG	1 = Included
		transactions

	G62	Number of IDSEL	C_NUM_	1 to 16	8	integer
	G62	signals supported	IDSEL	1 to 16	8	integer
		signals supported	IDSEL

				31 down to 16
		PCI address bit that PCI	C_BRIDGE_	Must be <= 15 +
	G63	v3.0 core IDSEL is	IDSEL_ADDR_	C_NUM_IDSEL.	16	integer
		connected to	BIT	AD(31 down to 0) index
				labeling

			IPIF Parameters Group

		PLB master ID bus	C_PLB_MID_	log2(C PLB NUM MA
	G64	width (set automatically	C_PLB_MID_	log2(C PLB NUM MA	3	integer
		by XPS)	WIDTH	STERS)
		by XPS)

		Number of masters on	C_PLB_NUM
	G65	PLB bus (set	C_PLB_NUM	1-16	8	integer
	G65	PLB bus (set	MASTERS	1-16	8	integer
		automatically by XPS)	MASTERS
		automatically by XPS)

	G66	PLB Address width	C_PLB_	32 (only allowed value	32	integer
	G66	PLB Address width	AWIDTH	32 (only allowed value	32	integer
			AWIDTH

	G67	PLB Data width	C_PLB_	64 (only allowed value	64	integer
	G67	PLB Data width	DWIDTH	64 (only allowed value	64	integer
			DWIDTH

	G68	Specifies the target	C_FAMILY	See PLB IPIF data	virtex2	string
	G68	technology	C_FAMILY	sheet	virtex2	string
		technology		sheet

Notes:

1. The range specified must comprise a complete, contiguous power of two range, such that the range = 2n and the n least significant bits of the Base Address are zero.

2. The minimum address range specified by C BASEADDR and C HIGHADDR must be at least 0x1FF. C_BASEADDR must be a multiple of the range, where the range is C_HIGHADDR - C_BASEADDR + 1.

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 Cplbawidth BAR CPCIBAR2 IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision