Xilinx PLB PCI Full Bridge PLB PCI Transactions, Remote PLB Master PCI I/O Space PCI Memory Space

PLB PCI Full Bridge (v1.00a)

PLB PCI Transactions

The following subsections discuss details of the following types of transactions for the PLB PCI bridge to realize data throughputs as high as 132 MB/sec. This assumes the PLB clock is 100 MHz or higher. Lower data rates will be realized with lower PLB clock rates for some transactions.

•The section, PLB Master Initiates a Read Request of a PCI target, discusses the PLB master read of a PCI target where the v3.0 core is the PCI initiator.

•The section, PLB Master Initiates a Write Request to a PCI Target, discusses the PLB master write to a PCI target where the v3.0 core is the PCI initiator.

•The section, PCI Initiator Initiates a Read Request of a PLB Slave, discusses the remote PCI initiator read of a PLB device where the v3.0 core is the PCI target

•The section, PCI Initiator Initiates a Write Request to a PLB Slave, discusses the remote PCI initiator write to a PLB device where the v3.0 core is the PCI target.

•The section, Configuration Transactions, discusses PLB master read and write of a PCI target configuration space where the v3.0 core is the PCI initiator.

PLB transactions that are supported are limited to the subset of PLB transactions that are supported by the IPIF. This limitation is caused by the time-multiplexed architecture of the PCI bus where addressing is required to be incremented by 4 bytes per data phase. When operating as a master, the IPIF can either perform single transactions (i.e., 1-8 bytes) or bursts of an arbitrary length. The length is determined by the PCI initiator supplying the data and/or by how fast the PCI initiator supplies/accepts the data.

When the IPIF is operating as a PLB slave, it performs single transfers of 1-8 bytes, burst transfers of any number of double words, and 4, 8 or 16-word line transactions. The IPIF always performs line read requests on the IPIC with the address double word aligned, independent of the target word requested. This is required because the PCI time-multiplexed address and data bus requires sequential addressing. PCI commands that are supported include I/O read, I/O write, memory read, memory write, memory read multiple, memory read line, and memory write invalidate. Table 15 shows the translations of PLB transactions to PCI commands, while in Table 16 shows the translations of PCI commands to PLB transactions.

The PCI transactions that are supported is limited to a subset of all PCI transactions because some features on the PCI are not supported on the PLB. Specifically, dynamic byte enable during multiple data phase transfers is not supported in burst transactions on the PLB. The PLB supports only full double words in burst read and write transactions. It is the user’s responsibility to insure that all byte enables are asserted for remote PCI initiator transactions with multiple data phases.

The Sl_wait signal is utilized in bridge PLB slave responses because the latency in the bridge, and the possibly-slower PCI clock which would not allow completion of read operations prior to a PLB IPIF time-out. The IPIF has a timer limiting the bridge response time, however, the timer is inhibited when Sl_wait is asserted. Bus lock is utilized to eliminate arbitration cycles when appropriate.

Table 15: Translation Table for PLB transactions to PCI commands

Remote PLB Master	PCI I/O Space	PCI Memory Space	PCI Memory Space
	Prefetchable or
Transaction		Prefetchable	Non-prefetchable
	Non-prefetchable
Single Read (<=8 bytes)	I/O Read	Memory Read	Not Supported
Read Burst transfer double	I/O Read	Memory Read Multiple	Not Supported
word

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