Xilinx PLB PCI Full Bridge NET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33

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PLB PCI Full Bridge (v1.00a)

The constraints are also implemented automatically in the EDK tool flow with any tool option that invokes bridge synthesis. In this flow, tcl-scripts generate the ucf-file constraints and place them in a file in the OPB PCI Bridge directory of the project implementation directory. The ucf-file constraints are then included in the ngc-file generated in the EDK tool flow. The user can check the ucf-file in the implementation directory of the bridge directory to verify that the constraints are included. As noted above, the user can include all constraints in the top-level ucf-file. When the constraints are included in both the top-level ucf-file and the bridge ngc-file (via the bridge directory ucf-file), then the top-level ucf-file overrides any conflicting constraints in the bridge ngc-file.

To remind the user that the following constraints must be included, PLATGEN will generate the message:

The OPB PCI Bridge design requires design constraints to guarantee performance. Please refer to the OPB IPIF/LogiCORE PCI64 v3.0 bridge design data sheet for details.

Additional bridge specific constraints are required and an example ucf-file is provided in the EDK pcores library. To remind the user that the additional bridge related constraints must be included in the top-level ucf-file, PLATGEN will generate the message:

An example UCF is available for this core and must be modified for use in the system. Please refer to the EDK Getting Started guide for the location of this file.

The constraints that the LogiCORE PCI64 v3.0 core require to meet PCI specifications are shown below.

All io buffers must have IOB=TRUE

IOSTANDARD must explicitly list PCI33_3. Both BYPASS IOBDELAY=BOTH must be included for all PIC ports, as shown below.

NET "PCI AD(*)" IOSTANDARD=PCI33 3;

NET "PCI CBE(*)" IOSTANDARD=PCI33 3;

NET "PCI PAR" IOSTANDARD=PCI33 3; NET "PCI FRAME N" IOSTANDARD=PCI33 3; NET "PCI TRDY N" IOSTANDARD=PCI33 3; NET "PCI IRDY N" IOSTANDARD=PCI33 3; NET "PCI STOP N" IOSTANDARD=PCI33 3; NET "PCI DEVSEL N" IOSTANDARD=PCI33 3; NET "PCI PERR N" IOSTANDARD=PCI33 3; NET "PCI SERR N" IOSTANDARD=PCI33 3; #Include next 2 if routed to pins NET "IDSEL" IOSTANDARD=PCI33 3;

NET "GNT N" IOSTANDARD=PCI33 3;

NET "PCI AD(*)" BYPASS;

NET "PCI CBE(*)" BYPASS;

NET "PCI_PAR" BYPASS;

NET "PCI_FRAME_N" BYPASS;

NET "PCI_TRDY_N" BYPASS;

NET "PCI_IRDY_N" BYPASS;

NET "PCI_STOP_N" BYPASS;

NET "PCI_DEVSEL_N" BYPASS;

NET "PCI_PERR_N" BYPASS;

NET "PCI_SERR_N" BYPASS;

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DS508 March 21, 2006

 

 

Product Specification

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Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a System Reset Evaluation VersionFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType TYPE2 CIPIFBAR3HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthCPCIBAR2 BARIPIFBAR0 Cplbawidth LEN0PCI2IPIF Fifo Ctrigipif DEPTH-3. PCI2IPIFWrburst Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bus Interface I/O Signals Port Signal Name Interface DescriptionPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Cipifbarnum Ipif BARCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic Cpcibarnum CPCIBAR2IPIFBAR0CPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Command PLB PCI BridgeSupported PCI Bus Commands Code NameRegister Name PLB Address Access PLB PCI Bridge Register DescriptionsPLB PCI Bus Interface Registers Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Write Serr Enable- Enables this interrupt to PCI Initiator Read Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busPLB PCI Transactions Remote PLB Master PCI I/O Space PCI Memory SpaceTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision
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