Xilinx PLB PCI Full Bridge specifications 0x00 0xFF 0x01

PLB PCI Full Bridge (v1.00a)

Table 21: Results of v3.0 core Command Register configuration by remote host bridge (PCI-side) and by self-configuration (PLB-side)

	Results in Command Register after write
	(PLB-side byte swapped format)
Data Written (PLB-side byte	by remote host bridge	by self-configuration
swapped format)
0x0000	0x0000	0x4605
0x0100	0x0000	0x4605
0x0200	0x0200	0x4605
0x0300	0x0200	0x4605
0x0400	0x0400	0x4605
0x0500	0x0400	0x4605
0x8600	0x0600	0x4605
0x8700	0x0600	0x4605
0xFFFF	0x4605	0x4605

Notes:

1.This assumes that the PCI BARs in the v3.0 core are configured to only Memory type and not IO-type which is not an allowed configuration. After self-configuration, a remote initiator can reconfigure the v3.0 core to any valid state.

Table 22: Results of v3.0 core Latency Timer Register configuration by remote host bridge (PCI-side) and by self-configuration (PLB-side)

	Results in Latency Timer Register after write
	(PLB-side byte swapped format)
Data Written	by remote host bridge	by self-configuration
0x00	0x00	0xFF
0x01	0x01	0xFF
0xFF	0xFF	0xFF

Table 21 and Table 22 show examples only and do not show all the possible bit patterns. Note that the bytes are swapped for maintaining byte addressing integrity.

The v3.0 core is PCI 2.2 compliant core, but it has PCI 2.3 compliant features. The v3.0 core documentation should be reviewed for details of compliance.

Configuration transactions from the PLB-side of the bridge are supported by the PLB PCI bridge. The protocol follows the PCI 2.2 specification but with changes required to adapt to the PLB-side bus protocol. The primary difference is that all registers (Configuration Address Port, Configuration Data Port, and Bus Number/Subordinate Bus Number) are on the PLB-side of the bridge and are not accessible from the PCI-side via I/O transactions on the PCI bus. This approach is adopted so that one BAR of the v3.0 core is not required for the Configuration Port registers. The registers are mapped relative to the bridge device base address as shown in Table 5. The registers exist only if the bridge is configured with PCI host bridge configuration functionality.

Data is loaded in the Configuration Address Port with the Byte format specified in the PCI 2.2. specification. A PLB-side read of the Configuration Data Port initiates a Configuration Read command with data returned to the PLB-side upon completion of the PCI-side read command. A PLB-side write

48	www.xilinx.com	DS508 March 21, 2006
		Product Specification