Xilinx PLB PCI Full Bridge PLB PCI Bridge Register Descriptions, Register Name PLB Address Access

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						PLB PCI Full Bridge (v1.00a)

		Table 4: Supported PCI Bus Commands

			1101	Dual Address Cycle	Ignore	No

			1110	Memory Read Line	Yes	No

			1111	Memory Write Invalidate	Yes	No

PLB PCI Bridge Register Descriptions

The PLB PCI Bridge contains addressable registers for read/write operations as shown in Table 5. The base address for these registers is set by the base address parameter (C_BASEADDR). The address of each register is then calculated by an offset to the base address as shown in Table 5. Registers that reside in the user area of the PCI configuration header are mirrored in the IPIF register space as read-only registers; this is included for debug utility. The registers that exist in a given PLB PCI bridge depend on the configuration of the bridge.

Table 5: PLB PCI Bus Interface Registers

Register Name	PLB Address		Access

Device Interrupt Status Register (ISR)	C BASEADDR +	0x00	Read/TOW

Device Interrupt Pending Register (IPR)	C BASEADDR + 0x04		Read/Write

Device Interrupt Enable Register (IER)	C BASEADDR + 0x08		Read/Write

Device Interrupt ID (IID)	C BASEADDR + 0x18		Read

Global Interrupt Enable Register (GIE)	C BASEADDR + 0x1C		Read/Write

Bridge Interrupt Register	C BASEADDR + 0x20		Read/TOW

Bridge Interrupt Enable Register	C BASEADDR + 0x28		Read/Write

Reset Module	C BASEADDR + 0x80		Read/Write

Configuration Address Port	C BASEADDR + 0x10C		Read/Write

Configuration Data Port	C_BASEADDR + 0x110		Read/Write

Bus Number/Subordinate Bus Number	C_BASEADDR + 0x114		Read/Write

IPIFBAR2PCIBAR_0 high-order bits	C_BASEADDR + 0x180		Read/Write

IPIFBAR2PCIBAR 1 high-order bits	C_BASEADDR + 0x184		Read/Write

IPIFBAR2PCIBAR 2 high-order bits	C_BASEADDR + 0x188		Read/Write

IPIFBAR2PCIBAR 3 high-order bits	C_BASEADDR + 0x18C		Read/Write

IPIFBAR2PCIBAR 4 high-order bits	C_BASEADDR +	0x190	Read/Write

IPIFBAR2PCIBAR 5 high-order bits	C_BASEADDR +	0x194	Read/Write

Host Bridge device number	C_BASEADDR + 0x198		Read/Write

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 Cpcibarnum CPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB SlaveAbnormal condition Memory Read Memory Read Multiple Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History