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| PLB PCI Full Bridge (v1.00a) |
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| Table 4: Supported PCI Bus Commands |
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| 1101 | Dual Address Cycle | Ignore | No |
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| 1110 | Memory Read Line | Yes | No |
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| 1111 | Memory Write Invalidate | Yes | No |
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PLB PCI Bridge Register Descriptions
The PLB PCI Bridge contains addressable registers for read/write operations as shown in Table 5. The base address for these registers is set by the base address parameter (C_BASEADDR). The address of each register is then calculated by an offset to the base address as shown in Table 5. Registers that reside in the user area of the PCI configuration header are mirrored in the IPIF register space as
Table 5: PLB PCI Bus Interface Registers
Register Name | PLB Address | Access | |
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Device Interrupt Status Register (ISR) | C BASEADDR + | 0x00 | Read/TOW |
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Device Interrupt Pending Register (IPR) | C BASEADDR + 0x04 | Read/Write | |
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Device Interrupt Enable Register (IER) | C BASEADDR + 0x08 | Read/Write | |
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Device Interrupt ID (IID) | C BASEADDR + 0x18 | Read | |
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Global Interrupt Enable Register (GIE) | C BASEADDR + 0x1C | Read/Write | |
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Bridge Interrupt Register | C BASEADDR + 0x20 | Read/TOW | |
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Bridge Interrupt Enable Register | C BASEADDR + 0x28 | Read/Write | |
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Reset Module | C BASEADDR + 0x80 | Read/Write | |
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Configuration Address Port | C BASEADDR + 0x10C | Read/Write | |
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Configuration Data Port | C_BASEADDR + 0x110 | Read/Write | |
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Bus Number/Subordinate Bus Number | C_BASEADDR + 0x114 | Read/Write | |
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IPIFBAR2PCIBAR_0 | C_BASEADDR + 0x180 | Read/Write | |
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IPIFBAR2PCIBAR 1 | C_BASEADDR + 0x184 | Read/Write | |
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IPIFBAR2PCIBAR 2 | C_BASEADDR + 0x188 | Read/Write | |
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IPIFBAR2PCIBAR 3 | C_BASEADDR + 0x18C | Read/Write | |
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IPIFBAR2PCIBAR 4 | C_BASEADDR + | 0x190 | Read/Write |
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IPIFBAR2PCIBAR 5 | C_BASEADDR + | 0x194 | Read/Write |
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Host Bridge device number | C_BASEADDR + 0x198 | Read/Write | |
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DS508 March 21, 2006 | www.xilinx.com | 23 |
Product Specification