Xilinx PLB PCI Full Bridge specifications V3.0 Core Parameters Group, Configuration

Page 12

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

Parameter

Allowable Values

Default

VHDL

Description

Name

Value

Type

 

 

 

 

 

 

 

 

 

Number of IDELAY

C_NUM_

2-6

 

 

G50

controllers instantiated.

2

integer

IDELAYCTRL

(Virtex-4 only)

 

Ignored it not Virtex-4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Includes IDELAY

 

1=Include IDELAY

 

 

 

 

primitive

 

 

G51

primitive on GNT_N.

C_INCLUDE_

0

integer

 

Set by tcl-scripts and

GNT_DELAY

(Virtex-4 only)

 

 

 

 

ignored if not Virtex-4.

 

0=No IDELAY primitive

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Provides a means for

 

 

 

 

 

BSB to pass LOC

 

 

 

 

 

coordinates for

 

 

 

 

 

IDELAYCTRLs for a

 

See Device

 

 

 

given board to

C_IDELAY

Implementation section,

 

 

G52

EDK and is optional for

subsection Virtex-4

NOT SET

string

CTRL_LOC

 

user to set LOC

Support for allowed

 

 

 

 

 

 

 

constraints. This

 

values

 

 

 

parameter has no

 

 

 

 

 

impact on bridge

 

 

 

 

 

functionality.

 

 

 

 

 

 

 

 

 

 

 

 

v3.0 Core Parameters Group

 

 

 

 

 

 

 

 

 

PCI Configuration

 

 

 

std_logic_

G53

Space Header Device

C_DEVICE_ID

16-bit vector

0x0000

vector

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

C VENDOR_

 

 

std_logic_

G54

Space Header Vendor

16-bit vector

0x0000

ID

vector

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

C CLASS

 

 

std_logic_

G55

Space Header Class

24-bit vector

0x000000

CODE

vector

 

Code

 

 

 

 

 

 

 

 

 

 

 

 

 

G56

PCI Configuration

C REV ID

8-bit vector

0x00

std_logic_

Space Header Rev ID

vector

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

C SUB

 

 

std_logic_

G57

Space Header

16-bit vector

0x0000

SYSTEM ID

vector

 

Subsystem ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

C SUBSYSTE

 

 

std_logic_

G58

Space Header

M VENDOR_

16-bit vector

0x0000

vector

 

Subsystem Vendor ID

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

 

 

 

std_logic_

G59

Space Header

C MAX LAT

8-bit vector

0x0F

vector

 

Maximum Latency

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCI Configuration

 

 

 

std_logic_

G60

Space Header

C_MIN_GNT

8-bit vector

0x04

vector

 

Minimum Grant

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Configuration

 

 

 

 

 

 

 

 

12

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DS508 March 21, 2006

 

 

Product Specification

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Page 11 Page 13
Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a System Reset Evaluation VersionFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType TYPE2 CIPIFBAR3HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthCPCIBAR2 BARIPIFBAR0 Cplbawidth LEN0PCI2IPIF Fifo Ctrigipif DEPTH-3. PCI2IPIFWrburst Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bus Interface I/O Signals Port Signal Name Interface DescriptionPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Cipifbarnum Ipif BARCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic Cpcibarnum CPCIBAR2IPIFBAR0CPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Command PLB PCI BridgeSupported PCI Bus Commands Code NameRegister Name PLB Address Access PLB PCI Bridge Register DescriptionsPLB PCI Bus Interface Registers Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Write Serr Enable- Enables this interrupt to PCI Initiator Read Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busPLB PCI Transactions Remote PLB Master PCI I/O Space PCI Memory SpaceTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision
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