Xilinx PLB PCI Full Bridge specifications Abnormal Terminations

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PLB PCI Full Bridge (v1.00a)

burst write data from the PLB to PCI beyond the valid IPIF BAR address range. The PLB PCI Bridge does not support fast back-to-back PCI transactions.

Abnormal Terminations

In the context of the PLB PCI bridge, cacheline transactions are special cases of a burst. Abnormal terminations during a cacheline write operation have the same response as a burst write transaction. Recall that the PLB IPIF specification requires that the targetword of a cacheline write be the first word of the line.

•If a SERR error, including a parity error during the address phase, is detected on either a single or burst transfer, the PLB Master Write SERR interrupt is asserted. If the PLB transfer is in progress, Sl_MErr is asserted with Sl_wrDAck.

•If on either a single or burst write the PLB PCI Bridge asserts a master abort due to no response from a target, the PLB PCI Bridge asserts a PLB Master Write Master Abort interrupt. The IPIF2PCI FIFO will be flushed when the Master Abort Write interrupt is asserted. If the PLB transfer is in progress, Sl_MErr is asserted with Sl_wrDAck.

•If on a single transfer or on the first data cycle of a burst transfer a PCI retry from the PCI target occurs, the PLB PCI Bridge will automatically perform up to a parameterized number of retries. The number of retries is set by C_NUM_PCI_RETRIES IN WRITES. A parameterized wait time before a retry occurs is set by C_NUM_PCI_PRDS BETWN RETRIES IN WRITES. Both parameters are set at build time. During the time retries are possible, subsequent PLB master write operations to a PCI target will be inhibited by assertion of PLB rearbitrate. If the retries are not successful (i.e., disconnects or more PCI retries occur), a PLB Master Write interrupt identifying the failure mode will be asserted. The IPIF2PCI FIFO will be flushed upon asserting any of the three PLB Master Write Retry interrupts. Consistent with the PCI Spec, the PLB master is required to perform the write again if the last of the automatic retries was terminated with a PCI retry.

•If on a single transfer the target disconnects with data, the transfer will be completed.

•If the target disconnects, either with or without data after the first data phase of a burst transfer, the IPIF/v3.0 core terminates the PCI transaction. If the IPIF2PCI FIFO is not empty, another PCI transaction is attempted. Due to pipelining in the v3.0 core, the IPIF2PCI FIFO must backup 1-3 words, depending on the type of target disconnect. The PLB PCI Bridge performs up to a parameterized number of retries (C NUM_PCI_RETRIES_IN_WRITES). A parameterized wait time (C_NUM PCI PRDS BETWN RETRIES_IN_WRITES) before a retry occurs is included. Both parameters are set at build time and are the same as defined for PCI retry situation. During the time retries are in progress, subsequent PLB master write operations to a PCI target are inhibited. If the PCI transaction retries are not successful due to any combination of PCI retries, disconnection, or time out, a PLB Master Write Retry interrupt, PLB Master Write Retry Disconnect interrupt, or PLB Master Write Retry Timeout interrupt, respectively, will be asserted. The actual interrupt that is asserted is defined by the type of disconnect that occurred on the last of the prescribed number of retries. The IPIF2PCI FIFO is flushed upon asserting one of the PLB Master Write interrupts. Consistent with the PCI Spec, the PLB master is required to perform the write again if the last of the automatic retries was terminated with a PCI retry.

•If on a single transfer or on a burst transfer a PERR error during data phase is detected, the PLB PCI Bridge aborts the PCI transaction and a PLB Master Write PERR interrupt is asserted. If the burst transfer is still in progress, an Sl_MErr is asserted with Sl_wrDAck. The IPIF2PCI FIFO is flushed upon asserting the PERR Write interrupt. The Detected Parity Error status register bit is set as well.

•If on a burst transfer, the initiator latency timer expires, the PLB PCI Bridge terminates the PCI

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision
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