Xilinx PLB PCI Full Bridge specifications Configuration Address Port Register Description

PLB PCI Full Bridge (v1.00a)

Configuration Address Port Register Description

The Configuration Address Port Register exists only if the bridge is configured with PCI host bridge configuration functionality (i.e., C_INCLUDE_PCI_CONFIG=1). This register is read/write with some bits hardwired as in Table 10. Definition of this register is a subset of the PCI 2.2. All accesses to the register are 32-bit accesses. Data is latched on a write in all 32-bits except where bits are hard-wired. A read yields all 32-bits. Reset clears all bits. Eight and sixteen bit accesses are not supported, therefore, such accesses are not passed on as IO accesses. Byte address integrity is maintained from PCI little endian word format when writing/reading data to/from the Configuration Address Port Register which is defined in big endian word format.

Table 10: Configuration Address Port Register Bit Definitions (Bit assignment assumes 32-bit bus)

Bit(s)	Name	Access	Reset	Description
			Value
0-5	D0-D5	Read/Write	0x0	Identifies the target word address (32bits) within the
				function’s configuration space (1-64)
6-7	D6-D7	Read	0x0	Hard-wired to 0, read-only
8-12	D8-D12	Read/Write	0x0	Identifies the target PCI Device (0-31)
13-15	D13-D15	Read/Write	0x0	Identifies the target function (1-8)
16-23	D16-D23	Read/Write	0x0	Identifies the target PCI Bus (1-256)
24	D24	Read/Write	0x0	Active high enable bit
25-31	D25-D31	Read	0x0	Reserved and hardwired to 0.

Configuration Data Port Register Description

The Configuration Data Port Register exists only if the bridge is configured with PCI host bridge configuration functionality (i.e., C INCLUDE PCI_CONFIG=1). This register is read/write and definition of this register follows PCI 2.2. All accesses to the register are 32-bit accesses. A read initiates a configuration read command and a write initiates a configuration write command. Determination of whether the command is a type 0 or type 1 depends on the comparison results of the bus number compare. The fields are defined in Table 11. Reset clears all bits. Byte address integrity is maintained from PCI little endian word format when writing/reading data to/from the Configuration Data Port register which is defined in big endian word format.

Table 11: Configuration Data Port Address Register Bit Definitions (Bit Assignment Assumes 32-bit Bus)

Bit(s)	Name	Access	Reset	Description
			Value
				Read or write causes automatic execution of Configuration
0-31	D0 - D31	Read/Write	0x0	Read Command or Configuration Write Command using
				address/bus information in the Configuration Address Port
				register.

Bus Number/Subordinate Bus Number Register Description

The Bus Number/Subordinate Bus Number Register exists only if the bridge is configured with PCI host bridge configuration functionality (i.e., C_INCLUDE_PCI_CONFIG=1). This register is read/write. All accesses to the register are 32-bit accesses. The bus number is an 8-bit value defining the primary

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