Xilinx PLB PCI Full Bridge specifications Design Debug, Design Contraints

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PLB PCI Full Bridge (v1.00a)

Design Debug

The OBP PCI Bridge has a test vector output (PCI_monitor) to facilitate system debug (i.e., adding an ILA to a system). The test vector allows monitoring the PCI bus and is the output of IO-buffers that are instantiated in the LogiCORE v3.0 PCI core. PCLK, RCLK, and Bus2PCI_INTR are not included in the test vector because these signals do not have io-buffers instantiated in the Bridge and are accessible to use directly at the core top-level or above. If the port is not connected in the EDK tool top-level mhs-file, the wrapper simply leaves this port open. PCI Bus monitoring test vector bit definition is listed in Table 24.

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Table 24: PCI Bus Monitoring Signals

Bit Index		Signal Name		Instantiated IO-Buffer

		PCI Transaction Control Signals

0		FRAME_N		Yes

1		DEVSEL_N		Yes

2		TRDY_N		Yes

3		IRDY_N		Yes

4		STOP_N		Yes

5		IDSEL		Yes

		PCI Interrupt Signals

6		INTR_A		Optional

		PCI Error Signals

7		PERR_N		Yes

8		SERR_N		Yes

		PCI Arbitration Signals

9		REQ N		Optional

10		GNT N		No

	PCI Address, Data Path, and Command Signals

11		PAR		Yes

12-43		AD[31:0]		Yes

44-47		CBE[3:0]		Yes

Design Verification

The PLB PCI Bridge design will be verified according to IPSPEC000 PLB PCI Bridge Verification Plan.

Design Contraints

The OPB PCI Bridge uses the LogiCORE PCI64 v3.0 core that requires specific constraints to meet PCI specifications. UCF-files with the constraints for the LogiCORE PCI64 v3.0 core in many different packages are available from the LogiCORE Lounge. The PCI64 v3.0 core specific constraints can be included in the top-level ucf-file by the user.

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision