Xilinx PLB PCI Full Bridge PLB PCI Bridge Parameters-Port Dependencies Contd Generic

Page 19

 

 

 

 

 

 

 

PLB PCI Full Bridge (v1.00a)

 

 

 

 

 

 

 

 

 

 

Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)

 

 

 

 

 

 

 

 

 

 

 

 

Generic

Parameter

Affects

Depends

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G1, G10,

Meaningful only if G48 = 0 and G1>2. In

 

 

 

G12

C_IPIFBAR2PCIBAR_2

 

G11 and

this case only high-order bits that are the

 

 

 

 

 

 

G48

same in G10 and G11 are meaningful.

 

 

 

 

 

 

 

 

 

 

 

G13

C_IPIF_SPACETYPE_2

 

G1

Meaningful only if G1>2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>3, then G14 to

 

 

 

G14

C_IPIFBAR_3

G15

G1 and

G15 define the range in PLB-memory

 

 

 

G15

space that is responded to by this device

 

 

 

 

 

 

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>3, then G14 to

 

 

 

G15

C_IPIFBAR_HIGHADDR_3

G14

G1 and

G15 define the range in PLB-memory

 

 

 

G14

space that is responded to by this device

 

 

 

 

 

 

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G1, G14,

Meaningful only if G48 = 0 and G1>3. In

 

 

 

G16

C_IPIFBAR2PCIBAR_3

 

G15 and

this case only high-order bits that are the

 

 

 

 

 

 

G48

same in G14 and G15 are meaningful.

 

 

 

 

 

 

 

 

 

 

 

G17

C_IPIF_SPACETYPE_3

 

G1

Meaningful only if G1>3

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>4, then G18 to

 

 

 

G18

C_IPIFBAR_4

G19

G1 and

G19 define the range in PLB-memory

 

 

 

G19

space that is responded to by this device

 

 

 

 

 

 

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>4, then G18 to

 

 

 

G19

C_IPIFBAR_HIGHADDR_4

G18

G1 and

G19 define the range in PLB-memory

 

 

 

G18

space that is responded to by this device

 

 

 

 

 

 

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G1, G18,

Meaningful only if G48 = 0 and G1>4. In

 

 

 

G20

C_IPIFBAR2PCIBAR_4

 

G19 and

this case only high-order bits that are the

 

 

 

 

 

 

G48

same in G6 and G7 are meaningful.

 

 

 

 

 

 

 

 

 

 

 

G21

C_IPIF_SPACETYPE_4

 

G1

Meaningful only if G1>4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1=6, then G6 to G7

 

 

 

G22

C_IPIFBAR_5

G23

G1 and

define the range in PLB-memory space

 

 

 

G23

that is responded to by this device (IPIF

 

 

 

 

 

 

 

 

 

 

 

 

 

BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1=6, then G6 to G7

 

 

 

G23

C_IPIFBAR HIGHADDR_5

G22

G1 and

define the range in PLB-memory space

 

 

 

G22

that is responded to by this device (IPIF

 

 

 

 

 

 

 

 

 

 

 

 

 

BAR)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G1, G22,

Meaningful only if G48 = 0 and G1=6. In

 

 

 

G24

C IPIFBAR2PCIBAR_5

 

G23 and

this case only high-order bits that are the

 

 

 

 

 

 

G48

same in G22 and G23 are meaningful.

 

 

 

 

 

 

 

 

 

 

 

G25

C IPIF_SPACETYPE_5

 

G1

Meaningful only if G1=6

 

 

 

 

 

 

 

 

DS508 March 21, 2006

www.xilinx.com

19

Product Specification

Image 19
Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision