Xilinx specifications PLB PCI Full Bridge v1.00a

Page 38

PLB PCI Full Bridge (v1.00a)

when an incomplete PCI transactions occur or when PCI errors occur. Details of the abnormal terminations are discussed in a later section. In these transactions, the v3.0 core is the PCI initiator.

The operation is essentially the same whether the PCI space is memory or I/O space; the only difference is the command sent to the v3.0 core by the PLB PCI Bridge. The bridge can accept both fixed length and arbitrary length burst transactions on the PLB. All PLB burst transfers are 64-bits per data phase; dynamic byte enable is not supported by the PLB protocol. The length of a burst defined as arbitrary length is defined by the master signal PLB_wrBurst. The PLB specification requires all cacheline write transactions to be sequential fill type, independent of the target word; however, the PLB IPIF requires the address received during a cacheline write operation to be the first word of the line being written.

Commands supported in PLB master write operations are I/O write and memory write (both single and burst). The command used is based on the address/qualifier decode, which includes the address, memory type (i.e., I/O or memory type), if a double word is written and if PLB wrBurst is asserted. Table 15 shows translations of PLB transactions to PCI commands.

The address presented on the PLB is translated to the PCI address space by high-order bit substitution with the 2 lsbs set as follows. If the target PCI address space is memory space, the 2 lsbs are set to 00 (i.e., linear incrementing mode). If the PCI target address space is IO-space, the 2 LSBs are passed unchanged from that presented on the PLB bus.

Both single and burst write transfers are posted so the data is buffered in the IPIF2PCI FIFO, which has a depth defined by the parameter C_IPIF2PCI_FIFO ABUS WIDTH. Due to the FIFO backup requirement of the v3.0 core, the FIFO usable buffer depth is the actual depth minus 3 words.

Data is loaded in the FIFO on each clock cycle that the write request is asserted and the address decode is valid. If the transaction is not a burst (i.e., PLB_wrBurst is not high), two cases can occur because the PLB bus is 64-bit and the PCI bus is 32-bit. If the PLB transfer is a single word or bytes within a single word, a single PCI transaction (I/O or Memory Write command) is performed. If the PLB transfer is a double word or bytes within both words of the double word, a burst of 2 words is performed on the PCI bus. In PLB burst transfers (i.e., PLB wrBurst is asserted), the data is buffered and the PCI transfer is initiated when the FIFO is filled to the level defined by the parameter

C_TRIG_PCI DATA XFER OCC LEVEL or when the PLB write is completed.

Only one PLB master write to a PCI target is supported at a time. Write transactions are not queued in the bridge. After the PLB write to the bridge is completed and while a write to PCI is being completed, the PLB PCI Bridge asserts PLB rearbitrate to terminate subsequent PLB transactions. When a posted write is complete, another write request from a PLB master can be initiated.

Consistent with the PCI specification, the PLB PCI Bridge re-issues commands when an PCI retry is asserted. To avoid permanent livelock, the posted write is attempted to be completed up to a predefined number of retries defined by the parameter C_NUM_PCI_RETRIES_IN_WRITES. Re-issuing the write operation on the PCI is automatic.

It is the responsibility of the master to properly write data to a PCI target from non-prefetchable PLB sources. For example, it must perform single transaction reads of non-prefetchable PLB sources to avoid loss of data in fire-and-forget writes to a PCI target.

In addition, the user must insure that any burst writes do not attempt to write beyond a valid address range. The PLB IPIF does not check for valid address during data phases. Therefoe, during a burst, it will accept data that is correlated to an address beyond the current range. The PLB PCI Bridge will transfer the data on the PCI if it is received without error flagging. It is the user’s responsibility not to

38

www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

Page 37 Page 39
Image 38
Page 37 Page 39
Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 CplbawidthIPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code NamePLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busTransaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB SlaveAbnormal condition Memory Read Memory Read Multiple Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History
Top Page Image Contents