Xilinx PLB PCI Full Bridge specifications System Reset, Evaluation Version, Functional Description

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PLB PCI Full Bridge (v1.00a)

System Reset

When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock periods of the slowest clock.

Evaluation Version

The PLB PCI Bridge is delivered with a hardware evaluation license. When programmed into a Xilinx device, the core will function in hardware for about 8 hours at the typical frequency of operation. To use the PLB PCI Bridge without this timeout limitation, a full license must be purchased.

Functional Description

The PLB PCI Bridge design is shown in Figure 1 and described in the following sections. As shown, PLB IPIF PCI Bridge is comprised of three main modules:

The PLB IPIF (Processor Local Bus Intellectual Property InterFace). It interfaces to the PLB bus.

The IPIF v3.0 Bridge. It interfaces between the PLB IPIF and the v3.0 core.

The LogiCORE PCI32 Interface v3.0 core. It interfaces to the PCI bus.

PLB IPIF

IPIF/V3 Bridge

 

 

 

Interrupt

 

Bridge

 

Module

 

Registers

 

Bus

 

 

 

PLB

 

 

 

 

ave SM

PCI2IPIF

Initiator

Slave

FIFO

 

Attachment

IPIF2PCI

 

Sl

FIFO

 

 

 

 

 

PCI2IPIF

 

 

Master

FIFO

 

 

Attachment

IPIF2PCI

 

Target

 

 

 

FIFO

 

 

 

 

 

 

Master SM

 

Figure 1: PLB PCI Full Bridge Block Diagram

Xilinx

v3.0 PCI Core

PCI Bus

ds508_01_112205

LogiCore Version 3.0 32-bit PCI Core Requirements

The PLB PCI bridge uses the 32-bit Xilinx LogiCore Version 3 IP core. Before the bridge can perform transactions on the PCI bus, the v3.0 core must be configured via configuration transactions from either the PCI-side or if configuration functionality is included in the bridge configuration, from the PLB-side. Both a design guide and an implementation guide are available for the Xilinx LogiCore v3.0 PCI IP

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www.xilinx.com

DS508 March 21, 2006

 

 

Product Specification

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Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a System Reset Evaluation VersionFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType TYPE2 CIPIFBAR3HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthCPCIBAR2 BARIPIFBAR0 Cplbawidth LEN0PCI2IPIF Fifo Ctrigipif DEPTH-3. PCI2IPIFWrburst Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bus Interface I/O Signals Port Signal Name Interface DescriptionPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Cipifbarnum Ipif BARCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic Cpcibarnum CPCIBAR2IPIFBAR0CPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Command PLB PCI BridgeSupported PCI Bus Commands Code NameRegister Name PLB Address Access PLB PCI Bridge Register DescriptionsPLB PCI Bus Interface Registers Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Write Serr Enable- Enables this interrupt to PCI Initiator Read Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busPLB PCI Transactions Remote PLB Master PCI I/O Space PCI Memory SpaceTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision