Xilinx specifications PLB PCI Full Bridge v1.00a

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PLB PCI Full Bridge (v1.00a)

default in all transfers. Address translation is performed by high-order bit substitution. High-order bit definition is defined only by parameters

•Registers include

-Interrupt and interrupt enable registers at different hierarchal levels

-Reset

-Configuration Address Port, Configuration Data Port and Bus Number/Subordinate Bus Number

-High-order bits for PLB to PCI address translation

-Bridge Device number on PCI bus

•PLB-side Interrupts include

-PLB Master Read SERR and PERR

-PLB Master Read Target Abort

-PLB Master Write SERR and PERR

-PLB Master Write Target Abort

-PLB Master Write Master Abort

-PLB Master Burst Write Retry and Retry Disconnect

-PLB Master Burst Write Retry Timeout

-PCI Initiator Read and Write SERR

•Asynchronous FIFOs with backup capability

•Synchronization circuits for signals that cross time-domain boundaries

•Responds to the PCI latency timer

•Completes posted write operations prior to initiating new operations

•Signal set required for integrating a PCI bus arbiter in the FPGA with the PLB PCI bridge is available at the top-level of the PLB PCI bridge module. The signal set includes PCLK, RST_N, FRAME_I, REQ_N_toArb and IRDY I

•Supports PCI clock generated in FPGA

•Parameterized control of IO-buffer insertion of INTR_A and REQ_N IO-buffers

•All address translations performed by high-order bit substitution. The number of bits substituted depends on the address range

-Parameterized selection of IPIF BAR high-order bits defined by programmable registers for dynamic translation operation or by parameters for reduced resource utilization

•Parameterized selection of device ID number (when configuration functionality is included) defined by a programmable register for dynamic device number definition or by parameter to reduce resource utilization

•The PLB PCI bridge does not have an integral DMA

•Input signal to provide the means to asynchronous asset INTR_A from a user supplied register (i.e., a PLB GPIO). The signal is Bus2PCI_INTR is an active high signal

•PCI Monitor output port to monitor PCI bus activity

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision