Xilinx PLB PCI Full Bridge Cipifbarnum, Ipif BAR, CIPIFBARHIGHADDR0, CIPIFBAR2PCIBAR0

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PLB PCI Full Bridge (v1.00a)

Port and Parameter Dependencies

The dependencies between the IPI v3.0 Bridge design port (i.e., I/O signals) and parameters are shown in Table 1.

Table 3: PLB PCI Bridge Parameters-Port Dependencies

Generic

Parameter

Affects

Depends

Description

 

 

 

 

 

 

Bridge Features Parameter Group

 

 

 

 

 

 

 

 

 

The set of PLB/IPIF BAR-parameters of

 

 

 

 

N = 0 to C_IPIFBAR_NUM-1 are

 

 

 

 

meaningful. When C IPIFBAR NUM <

 

 

 

 

6, the parameters of N =

G1

C_IPIFBAR_NUM

G5-G25

 

C IPIFBAR NUM up to and including 5

 

 

 

 

have no effect. If C IPIFBAR NUM = 6,

 

 

 

 

the set of PLB/IPIF BAR-parameters of N

 

 

 

 

= 0 to 5 are all meaningful (i.e., G2-G25

 

 

 

 

are meaningful).

 

 

 

 

 

 

 

 

 

G2 to G3 define range in PLB-memory

G2

C_IPIFBAR_0

G3

G3

space that is responded to by this device

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

G2 to G3 define range in PLB-memory

G3

C_IPIFBAR_HIGHADDR_0

G2

G2

space that is responded to by this device

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

G2, G3 and

Meaningful only if G48 = 0 and in this

G4

C_IPIFBAR2PCIBAR_0

 

case only high-order bits that are the

 

G48

 

 

 

same in G2 and G3 are meaningful.

 

 

 

 

 

 

 

 

 

G5

C_IPIF_SPACETYPE_0

 

 

 

 

 

 

 

 

 

 

 

 

Meaningful only if G1>1, then G6 to G7

G6

C IPIFBAR 1

G7

G1 and G7

define the range in PLB-memory space

that is responded to by this device (IPIF

 

 

 

 

 

 

 

 

BAR)

 

 

 

 

 

 

 

 

 

Meaningful only if G1>1, then G6 to G7

G7

C IPIFBAR HIGHADDR 1

G6

G1 and G6

define the range in PLB-memory space

that is responded to by this device (IPIF

 

 

 

 

 

 

 

 

BAR)

 

 

 

 

 

 

 

 

G1, G6, G7

Meaningful only if G48 = 0 and G1>1. In

G8

C IPIFBAR2PCIBAR 1

 

this case only high-order bits that are the

 

and G48

 

 

 

same in G6 and G7 are meaningful.

 

 

 

 

 

 

 

 

 

G9

C IPIF SPACETYPE 1

 

G1

Meaningful only if G1>1

 

 

 

 

 

 

 

 

 

Meaningful only if G1>2, then G10 to

G10

C IPIFBAR 2

G11

G1 and

G11 define the range in PLB-memory

G11

space that is responded to by this device

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

 

 

 

 

Meaningful only if G1>2, then G10 to

G11

C_IPIFBAR_HIGHADDR_2

G10

G1 and

G11 define the range in PLB-memory

G10

space that is responded to by this device

 

 

 

 

 

 

 

(IPIF BAR)

 

 

 

 

 

18

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DS508 March 21, 2006

 

 

Product Specification

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Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 CplbawidthIPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code NamePLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busTransaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision
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