Xilinx PLB PCI Full Bridge specifications Translation Table for PCI commands to PLB transactions

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PLB PCI Full Bridge (v1.00a)

Table 15: Translation Table for PLB transactions to PCI commands (Contd)

Sequential Read, 4, 8 and

I/O Read

Memory Read Multiple

Not Supported

16-word cacheline read (1)

 

 

 

Single Write (<=8 bytes)

I/O Write

Memory Write

Not Supported

 

 

 

 

Write Burst transfer double

I/O Write

Memory Write (multiple

Not Supported

word

data phase)

 

 

 

 

 

 

Sequential fill, 4, 8 and

I/O Write

Memory Write (multiple

Not Supported

16-word cacheline write (2)

data phase)

 

 

Notes:

 

 

 

1.The PLB IPIF aligns the address on the IPIC to a double word boundary which is then presented on the PCI bus. This is independent of the target word presented.

2.The 405 always sources the first word on the line (i.e., sequential fill) on write.

Table 16: Translation Table for PCI commands to PLB transactions

PCI Initiator Command

PLB Memory Prefetchable

PLB Memory Non-prefetchable

 

 

 

I/O Read

Not Supported

Not Supported

 

 

 

I/O Write

Not Supported

Not Supported

 

 

 

Memory Read

PLB Single Read

Not Supported

 

 

 

Memory Read Multiple

PLB Burst Read with all BE asserted (1)

Not Supported

Memory Read Line

PLB Single Read

Not Supported

 

 

 

Memory Write

PLB Single Write

Not Supported

(single data phase)

 

 

 

 

 

Memory Write 2

PLB Burst Write of length defined by

Not Supported

(multiple data phase)

available data in FIFO (2)

 

Memory Write Invalidate

PLB Burst Write

Not Supported

 

 

 

Notes:

1.The PLB does not support dynamic byte enable (BE) in burst read transactions so when Memory Read Multiple is translated to a PLB burst read, all BE are asserted during the PLB read operation.

2.The PLB does not support dynamic byte enable (BE) in burst write transactions so when Memory Write Multiple is translated to a PLB burst write, all BE are asserted during the PLB write operation.

For all the transactions listed above, the following design requirements are specified:

•Both PCI and PLB clocks will be independent global buffers. For Virtex-4, RCLK must also be driven by global buffer.

•The PLB clock can be slower or faster than the PCI clock. For Virtex-4, RCLK must be 200 MHz.

•Address space on the PCI side accessible from the PLB side must be translated to a 2N contiguous block on the PLB side. Up to six independent blocks are possible. Each block has parameters for base address (BAR), high address which must define a 2N range, address translation vector, and memory designator (memory or I/O).

•All address space on the PLB side that is accessible from the PCI side must be translated to a maximum of three 2N contiguous blocks on the PCI side. Up to three independent blocks are possible because the LogiCore PCI v3.0 core supports up to 3 BARs. Each block has parameters for length which must be a 2N range, and address translation vector. Only memory space in the sense of PCI memory space is supported. Space type is mirrored in the PCI configuration registers.

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthBAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision
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