Xilinx PLB PCI Full Bridge specifications Configuration Space Header

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PLB PCI Full Bridge (v1.00a)

bridge is not used. As with Memory and IO data transactions, byte addressing integrity is maintained in configuration transfers across the bus.

When host bridge configuration functionality is implemented in the PLB PCI bridge, the v3.0 core in the PLB PCI bridge must be configured first. The minimum that must be set is the Bus master enable bit in the command register and the latency timer register. This requirement is because the v3.0 core has the capability to configure only itself until the Bus master enable bit is set in the command register of the v3.0 core and the latency timer register is properly set to avoid timeouts. If the v3.0 core latency timer is set to 0 value, configuration writes to remote PCI devices will not complete and configuration reads of remote PCI devices will terminate due to the latency timer expiration. Configuration reads of remote PCI devices with the latency timer set to 0 will return 0xFFFFFFFF.

Table 21 shows the results of configuring the v3.0 core configuration header in the PLB PCI bridge by both PLB-side configuration transactions and by remote PCI host bridge configuration transactions from the PCI-side. This example assumes all PCI BARs are designated memory space which is the only allowed PCIBAR memory type. Note that PLB-side configuration of the v3.0 core enables all functionality in the Command Status Register and sets the latency timer to maximum count for most any data value written to the registers. This behavior is an artifact of the v3.0 core behavior.

Configuration Space Header

The LogiCORE v3.0 core used in the PLB PCI bridge can be configured with functionality to address a wide range of applications.

Fields of the Configuration Space Header are Device ID, Vendor ID, Class Code, Rev ID, Subsystem ID, Subsystem Vendor ID, Maximum Latency and Minimum Grant. The parameters for these fields are C_DEVICE_ID, C_VENDOR_ID, C_CLASS_CODE, C REV ID, C SUBSYSTEM ID, C_SUBSYSTEM_VENDOR_ID, C_MAX_LAT, C MIN GNT, respectively.

Listed below are details on the remaining configuration registers that are fixed in value.

BIST, Line Size and Expansion ROM Base Address are not implemented in the LogiCORE v3.0 design.

Header Type is a fixed byte of all zeros in the LogiCORE v3.0 design.

Cardbus CIS Pointer is set to all zeros for the LogiCORE v3.0 implementation used in the PLB PCI bridge.

Capabilities Pointer is not enabled for the LogiCORE v3.0 implementation used in the PLB PCI bridge.

Interrupt Pin register is set to 0x01.

BAR3, BAR4 and BAR5 are not supported by the LogiCORE v3.0 Core. For these registers and unimplemented PCIBARs (determined by C_PCIBAR_NUM), zeros are returned when read. Writes to the unimplemented configuration space addresses have no effect.

Latency timer, BAR0, BAR1, and BAR2 are required to be set by the host bridge as necessary. The number of BARs (0-3) is set by the parameter C_PCIBAR_NUM.

The User Configuration Space is enabled for the LogiCORE v3.0 implementation used in the PLB PCI bridge.

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read Multiple Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History
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