Xilinx PLB PCI Full Bridge specifications PLB Master Write Master Abort- Interrupt25 indicates

PLB PCI Full Bridge (v1.00a)

Table 8: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus) (Contd)

Bit(s)	Name	Access	Reset	Description
			Value
	PLB Master	Read/Write		PLB Master Write Master Abort- Interrupt(25) indicates
25	Write Master		0x0	that the PLB PCI Bridge asserted a PCI master abort due to
		1 to clear
	Abort			no response from a target.
	PLB Master	Read/Write		PLB Master Write Target Abort- Interrupt(26) indicates a
26	Write Target		0x0	PCI target abort occurred during a PLB Master Write to a
		1 to clear
	Abort			PCI target.
27	PLB Master	Read/Write	0x0	PLB Master Write PERR- Interrupt(27) indicates a PERR
	Write PERR	1 to clear		error is detected on a PLB Master write to a PCI target.
	PLB Master	Read/Write		PLB Master Write SERR- Interrupt(28) indicates that a
28			0x0	SERR error was detected by the v3.0 core when performing
	Write SERR	1 to clear
				as a PCI initiator writing data to a PCI target.
	PLB Master	Read/Write		PLB Master Read Target Abort- Interrupt(29) indicates
29	Read Target		0x0	that a target abort was detected by the v3.0 core when
		1 to clear
	Abort			performing as a PCI initiator reading data from a PCI target.
	PLB Master	Read/Write		PLB Master Read PERR- Interrupt(30) indicates that a
30			0x0	PERR was detected by the v3.0 core when performing as a
	Read PERR	1 to clear
				PCI initiator reading data from a PCI target.
	PLB Master	Read/Write		PLB Master Read SERR- Interrupt(31) indicates that a
31			0x0	SERR error was detected by the v3.0 core when performing
	Read SERR	1 to clear
				as a PCI initiator reading data from a PCI target.

Bridge Interrupt Enable Register Description

The PLB PCI Bridge has interrupt enable features as described in IPSPEC048 PLB Device Interrupt Architecture. Bit assignment in the Bridge Interrupt Enable Register is shown in Table 9. The interrupt enable register is read/write. All bits are cleared upon reset.

Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)

Bit(s)	Name	Access	Reset			Description
			Value
0-18		Read	0x0	Unassigned-
				PCI Initiator Write SERR Enable- Enables this interrupt to
19	PCI Initiator	Read/Write	0x0	be passed to the interrupt controller.
	Write SERR			•	0	- Not enabled.
				•	1	- Enabled.
				PCI Initiator Read SERR Enable- Enables this interrupt to
20	PCI Initiator	Read/Write	0x0	be passed to the interrupt controller.
	Read SERR			•	0	- Not enabled.
				•	1	- Enabled.
21	Reserved		0x0	•	Reserved
	PLB Master			PLB Master Burst Write Retry Timeout Enable- Enables
				this interrupt to be passed to the interrupt controller.
22	Write Retry	Read/Write	0x0
				•	0	- Not enabled.
	Timeout
				•	1	- Enabled.

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