Xilinx PLB PCI Full Bridge Bar, IPIFBAR0 Cplbawidth, LEN0, CPCIBAR2IPI, FBAR1 PLB Awidth

Page 10

PLB PCI Full Bridge (v1.00a)

Table 1: PLB PCI Bridge Interface Design Parameters (Contd)

Generic

Feature /

Parameter

Allowable Values

Default

VHDL

Description

Name

Value

Type

 

 

 

 

 

 

 

 

 

IPIF BAR to which PCI

C_PCIBAR2

Vector of length

 

std_logic_

G27

BAR 0

0x00000000

 

is mapped

IPIFBAR_0

C_PLB_AWIDTH

 

vector

 

 

 

 

 

 

 

 

 

 

 

 

Power of 2 in the size in

C_PCIBAR_

 

 

 

G28

bytes of PCI BAR 0

5 to 29

16

integer

LEN_0

 

space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G29

IPIF BAR to which PCI

C_PCIBAR2IPI

Vector of length

0x00000000

std_logic_

 

BAR 1 is mapped

FBAR_1

C PLB AWIDTH

 

vector

 

 

 

 

 

 

 

Power of 2 in the size in

C_PCIBAR_

 

 

 

G30

bytes of PCI BAR 1

5 to 29

16

integer

LEN_1

 

space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G31

IPIF BAR to which PCI

C_PCIBAR2

Vector of length

0x00000000

std_logic_

 

BAR 2 is mapped

IPIFBAR_2

C PLB AWIDTH

 

vector

 

 

 

 

 

 

 

Power of 2 in the size in

C_PCIBAR_

 

 

 

G32

bytes of PCI BAR 2

5 to 29

16

integer

LEN_2

 

space

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G33

PCI address bus width

C_PCI_ABUS_

32

32

integer

WIDTH

 

 

 

 

 

 

 

 

 

 

 

G34

PCI data bus width

C_PCI_DBUS_

32

32

integer

WIDTH

 

 

 

 

 

 

 

 

 

 

 

 

Both PCI2IPIF FIFO

 

 

 

 

 

address bus widths.

C PCI2IPIF_

 

 

 

G35

Usable depth is

FIFO ABUS_

4-14

9

integer

 

2^C PCI2IPIF FIFO A

WIDTH

 

 

 

 

BUS WIDTH - 3

 

 

 

 

 

 

 

 

 

 

 

Both IPIF2PCI FIFO

 

 

 

 

 

address bus widths.

C IPIF2PCI_

 

 

 

G36

Usable depth is

FIFO ABUS_

4-14

9

integer

 

2^C IPIF2PCI FIFO A

WIDTH

 

 

 

 

BUS WIDTH - 3

 

 

 

 

 

 

 

 

 

 

 

Include explicit

 

 

 

 

G37

instantiation of INTR A

C INCLUDE_

0 = not included

1

integer

io-buffer (must be 1 to

INTR A BUF

1 = included

 

 

 

 

include io-buffer)

 

 

 

 

 

 

 

 

 

 

 

Include explicit

 

 

 

 

G38

instantiation of REQ N

C INCLUDE_

0 = not included

1

integer

io-buffer (must be 1 to

REQ N BUF

1 = included

 

 

 

 

include io-buffer)

 

 

 

 

 

 

 

 

 

 

 

Minimum PCI2IPIF

 

5 to the lesser of 24 or

 

 

 

FIFO occupancy level

C_TRIG_PCI_

the PCI2IPIF FIFO

 

 

 

that triggers the bridge

DEPTH-3. PCI2IPIF

 

 

G39

READ_OCC_

32

integer

to initiate a prefetch PCI

FIFO DEPTH given by

 

LEVEL

 

 

 

read of a remote PCI

2^C_PCI2IPIF_FIFO_

 

 

 

 

 

 

 

agent

 

ABUS_WIDTH

 

 

 

 

 

 

 

 

10

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DS508 March 21, 2006

 

 

Product Specification

Image 10
Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 CplbawidthIPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code NamePLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busTransaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision