Xilinx PLB PCI Full Bridge specifications PLB PCI Bridge Reset Register Description

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PLB PCI Full Bridge (v1.00a)

Table 9: Bridge Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus) (Contd)

	Bit(s)	Name	Access	Reset			Description
				Value


		PLB Master			PLB Master Burst Write Retry Disconnect Enable-
					Enables this interrupt to be passed to the interrupt controller.
	23	Write Retry	Read/Write	0x0
					•	0	- Not enabled.
		Disconnect
					•	1	- Enabled.


					PLB Master Write Retry Enable- Enables this interrupt to be
	24	PLB Master	Read/Write	0x0	passed to the interrupt controller.
		Write Retry			•	0	- Not enabled.

					•	1	- Enabled.

		PLB Master			PLB Master Write Master Abort Enable- Enables this
					interrupt to be passed to the interrupt controller.
	25	Write Master	Read/Write	0x0
					•	0	- Not enabled.
		Abort
					•	1	- Enabled.


		PLB Master			PLB Master Write Target Abort Enable- Enables this
					interrupt to be passed to the interrupt controller.
	26	Write Target	Read/Write	0x0
					•	0	- Not enabled.
		Abort
					•	1	- Enabled.


					PLB Master Write PERR Enable- Enables this interrupt to be
	27	PLB Master	Read/Write	0x0	passed to the interrupt controller.
		Write PERR			•	0	- Not enabled.

					•	1	- Enabled.

					PLB Master Write SERR Enable- Enables this interrupt to be
	28	PLB Master	Read/Write	0x0	passed to the interrupt controller.
		Write SERR			•	0	- Not enabled.

					•	1	- Enabled.

		PLB Master			PLB Master Read Target Abort Enable- Enables this
					interrupt to be passed to the interrupt controller.
	29	Read Target	Read/Write	0x0
					•	0	- Not enabled.
		Abort
					•	1	- Enabled.


					PLB Master Read PERR Enable- Enables this interrupt to be
	30	PLB Master	Read/Write	0x0	passed to the interrupt controller.
		Read PERR			•	0	- Not enabled.

					•	1	- Enabled.

					PLB Master Read SERR Enable- Enables this interrupt to be
	31	PLB Master	Read/Write	0x0	passed to the interrupt controller.
		Read SERR			•	0	- Not enabled.

					•	1	- Enabled.

PLB PCI Bridge Reset Register Description

The IP Reset module is always instantiated in the PLB PCI Bridge. Details on the IPIF Reset module can be found in the Processor IP Reference Guide. The IP Reset module permits the software reset of the PLB PCI Bridge, independently of other modules in the system. The MIR is not included.

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface Registers PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision