Xilinx PLB PCI Full Bridge Supported PCI Bus Commands, Command PLB PCI Bridge, Code Name

Page 22

PLB PCI Full Bridge (v1.00a)

Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)

Generic

Parameter

Affects

Depends

Description

 

 

 

 

 

 

 

 

 

If G61=0, G62 has no meaning. If

 

 

 

 

G61=1, G62 sets the number of devices

 

 

 

 

supported in configuration operations.

G62

C_NUM_IDSEL

G49 and

G61 and

Must be sufficiently large to include the

G63

G63

address bit defined by G63. If G49=1,

 

 

 

 

 

 

G62 restricts the allowed values that are

 

 

 

 

meaningful in the Device Number

 

 

 

 

Register

 

 

 

 

 

 

 

 

 

If G61=0 or G49=1, G63 has no

G63

C_BRIDGE_IDSEL_ADDR

G62

G49, G61

meaning. If G61=1 and G49=0, G63

_BIT

and G62

must be consistent with the setting of

 

 

 

 

 

 

G62

 

 

 

 

 

 

 

IPIF Parameters Group

 

 

 

 

 

 

G64

C_PLB_MID_WIDTH

 

 

 

 

 

 

 

 

G65

C_PLB_NUM_MASTERS

 

 

 

 

 

 

 

 

G66

C_PLB_AWIDTH

 

 

 

 

 

 

 

 

G67

C_PLB_DWIDTH

 

 

 

 

 

 

 

 

G68

C_FAMILY

G50-52

 

If G68 Virtex-4, G50-52 have no

 

meanings.

 

 

 

 

 

 

 

 

 

Supported PCI Bus Commands

The list of commands supported by the LogiCORE PCI interface is provided in Table 4.

Table 4: Supported PCI Bus Commands

 

Command

 

PLB PCI Bridge

 

 

 

 

 

Code

Name

Target

 

Initiator

 

 

 

 

 

0000

Interrupt Acknowledge

No

 

No

 

 

 

 

 

0001

Special Cycle

No

 

No

 

 

 

 

 

0010

I/O Read

No

 

Yes

 

 

 

 

 

0011

I/O Write

No

 

Yes

 

 

 

 

 

0100

Reserved

Ignore

 

Ignore

 

 

 

 

 

0101

Reserved

Ignore

 

Ignore

 

 

 

 

 

0110

Memory Read

Yes

 

Yes

 

 

 

 

 

0111

Memory Write

Yes

 

Yes

 

 

 

 

 

1000

Reserved

Ignore

 

Ignore

 

 

 

 

 

1001

Reserved

Ignore

 

Ignore

 

 

 

 

 

1010

Configuration Read

Yes

 

Optional

 

 

 

 

 

1011

Configuration Write

Yes

 

Optional

 

 

 

 

 

1100

Memory Read Multiple

Yes

 

Yes

 

 

 

 

 

22

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DS508 March 21, 2006

 

 

Product Specification

Image 22
Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 CplbawidthIPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code NamePLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busTransaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision