Xilinx specifications PLB PCI Full Bridge v1.00a

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PLB PCI Full Bridge (v1.00a)

to the Configuration Data Port register initiates a Configuration Write transaction on the PCI bus. Determination of whether the read or write transfer is type 0 or type 1 is done automatically.

Both type 0 and type 1 configuration transactions are supported. The type of transaction is determined from the Bus number in the Configuration Address Port register (Bits 8-15) and the bus numbers in the Bus Number/Subordinate Bus Number register. The local bus number is located at bits 8-15 and the maximum subordinate bus number is located at bits 24-31 in the Bus Number/Subordinate Bus Number register. If the Bus number in the Configuration Address Port register is equal to the local bus number in the Bus Number/Subordinate Bus Number register (bits 8-15), a type 0 transaction is performed. If the Bus number in the Configuration Address Port register is greater than the bus number in the Bus Number/Subordinate Bus Number register and less than or equal to the maximum subordinate Bus number, a type 1 transaction is performed. If a configuration transaction to a Bus Number not satisfying the inequality relation is attempted, then PLB Sl_MErr is asserted. When a configuration read from a bus number not in the subordinate bus range is initiated, nothing occurs on the PCI bus and an IPIF timout occurs with the IPIF asserting PLB Sl MErr. When a configuration write to a bus number not in the subordinate bus range is initiated, nothing occurs on the PCI bus, the data is discarded and PLB Sl_MErr is asserted. These conditions are equivalent to the situation where the master enable bit in the configuration command register of the v3.0 core is not set.

If a configuration read to a device number not assigned to a device on the PCI bus is attempted, a Master Abort occurs on the PCI bus, and all ones are returned on the PLB bus.

IDSEL is asserted for the device to be configured in all type 0 configuration transactions. The most common implementation method for IDSEL is used in this bridge implementation where address lines AD[31:16] are required to be mapped to IDSEL for each device.

The mapping is shown below.

•IDSEL of device 0 is connected to AD16

•IDSEL of device 1 is connected to AD17

•IDSEL of device 2 is connected to AD18.

•...

•IDSEL of device 15 is connected to AD31

A decode of the device number in the Configuration Address Port is used to determine which address line/IDSEL is asserted.

As noted, when the bridge has host bridge configuration functionality, IDSEL of the v3.0 core is connected internally to the AD-bit specified by the C_BRIDGE_IDSEL_ADDR_BIT parameter.

C_NUM_IDSEL specifies the number of PCI agents that can be configured on the PCI bus by specifying the number of IDSEL lines that are decoded and assigned to address lines AD[31:16]. Each device on the bus must have its IDSEL line properly connected to the PCI AD bus. It can be resistively-coupled to the associated address bit or direct coupling, if it is not detrimental to performance per PCI 2.2 specification. Because the v3.0 core does not support address stepping, resistive coupling of IDSEL with the assigned address bit must be sufficient to ensure proper signal levels at IDSEL without utilizing address stepping.

Multiple PLB PCI bridges can be instantiated on a given PLB. Each bridge has a unique base address with fixed offset to corresponding unique set of configuration registers. The unique set of configuration registers are used to perform configuration accesses on the unique primary PCI bus and its’

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthBAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision
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