Xilinx PLB PCI Full Bridge specifications Bits Name Access Reset Description

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PLB PCI Full Bridge (v1.00a)

Global Interrupt Enable Register Description

A global enable is provided to globally enable or disable interrupts from the PCI device. This bit is AND’d with the output to the interrupt controller. Bit assignment is shown in Table 7. Unlike most other registers, this bit is the MSB on the PLB. This bit is read/write and cleared upon reset.

Table 7: Global Interrupt Enable Register Bit Definitions (Bit assignment assumes 32-bit bus)

Bit(s)

Name

Access

Reset

 

Description

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Interrupt Global Enable- PLB bit (0) is the Interrupt

 

Interrupt Global

 

 

Global Enable bit. Enables all individually enabled

0

Read/Write

0x0

interrupts to be passed to the interrupt controller.

Enable

0 - Not enabled

 

 

 

 

 

 

 

 

 

 

 

1 - Enabled

 

 

 

 

 

1-31

 

Read

0x0

Unassigned-

 

 

 

 

 

 

Bridge Interrupt Register Description

The PLB PCI Bridge has twelve interrupt conditions. The Bridge Interrupt Enable Register enables each interrupt independently. Bit assignment in the Interrupt register for a 32-bit data bus is shown in Table 8. The interrupt register is read-only and bits are toggled by writing a 1 to the bit(s) being cleared. All bits are cleared upon reset. For more information, see the PLB IPIF Interrupt Product Specification; the module is labeled PLB Interrupt module, but is used in the PLB IPIF.

Table 8: Bridge Interrupt Register Bit Definitions (Bit Assignment Assumes 32-bit Bus)

Bit(s)

Name

Access

Reset

Description

Value

 

 

 

 

 

 

 

 

 

0-18

 

Read

0x0

Unassigned

 

 

 

 

 

 

PCI Initiator

Read/Write

 

PCI Initiator Write SERR- Interrupt(19) indicates a SERR

19

0x0

error was detected during a PCI initiator write of data to a

Write SERR

1 to clear

 

 

PLB slave.

 

 

 

 

 

 

 

 

 

 

PCI Initiator

Read/Write

 

PCI Initiator Read SERR- Interrupt(20) indicates a SERR

20

0x0

error was detected during a PCI initiator read of data from a

Read SERR

1 to clear

 

 

PLB slave.

 

 

 

 

 

 

 

 

 

21

Reserved

 

0x0

Reserved

 

 

 

 

 

 

PLB Master

 

 

PLB Master Burst Write Retry Timeout- Interrupt(22)

 

Read/Write

 

indicates the automatic PCI write retries were not

22

Write Retry

0x0

1 to clear

successful due to a latency timeout on the last retry during

 

Timeout

 

 

 

 

a PLB Master burst write to a PCI target.

 

 

 

 

 

 

 

 

 

 

PLB Master

 

 

PLB Master Burst Write Retry Disconnect- Interrupt(23)

 

Read/Write

 

indicates the automatic PCI write retries were not

23

Write Retry

0x0

1 to clear

successful due to a target disconnect on the last retry during

 

Disconnect

 

 

 

 

a PLB Master burst write to a PCI target.

 

 

 

 

 

 

 

 

 

 

 

 

 

PLB Master Write Retry- Interrupt(24) indicates the

24

PLB Master

Read/Write

0x0

automatic PCI write retries were not successful due to a PCI

Write Retry

1 to clear

retry on the last retry during a PLB Master burst write to a

 

 

 

 

 

 

PCI target.

 

 

 

 

 

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthBAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision