Xilinx PLB PCI Full Bridge Device Utilization and Performance Benchmarks, Bram# Gclk#

Page 57

PLB PCI Full Bridge (v1.00a)

the ucf-file in the implementation directory of the bridge directory to verify that the constraints are included. Alternatively, the user can include all constraints in the top-level ucf-file. When the constraints are included in both the top-level ucf-file and the bridge ngc-file (via the bridge directory ucf-file), then the top-level ucf-file overrides any conflicting constraints in the bridge ngc-file.

Device Utilization and Performance Benchmarks

Because the PLB PCI Bridge is a module that will be used with other design pieces in the FPGA, the utilization and timing numbers reported in this section are just estimates. As the PLB PCI Bridge is combined with other pieces of the FPGA design, the utilization of FPGA resources and timing of the PLB PCI Bridge design will vary from the results reported here.

In order to analyze the PLB PCI Bridge timing within the FPGA, a design was created that instantiated the PLB PCI bridge with the parameters set as outlined in Table 25. The data is shown for a Virtex-II Pro device; for Virtex-4devices and an additional GCLK is required for the RCLK 200 MHz signal.

Table 25: PLB PCI Bridge FPGA Performance and Resource Utilization Benchmarks

		Parameter Values					Device Resources					fMAX
Configuration	_IPIFBARC_NUM		__BARPCIC_NUM	___FIFOIPIF2PCICABUS_WIDTH	___FIFOPCI2IPIFCABUS_WIDTH	__PCIINCLUDEC _CONFIG	Slices	-FlipSliceFlops	input-4LUTs	BRAM#	GCLK#	MHz
Configuration
Description

Total (with BarOffset and	6		3		9	1	3336	2961	3868	8	2	>100
DevNumregs)	6		3		9	1	3336	2961	3868	8	2	>100
DevNumregs)

Total (with BarOffset and	6		3		5	1	3163	2729	3695	8	2	>100
DevNumregs)	6		3		5	1	3163	2729	3695	8	2	>100
DevNumregs)

Total (without BarOffset	6		3		9	1	3163	2805	3615	8	2	>100
and DevNum regs)	6		3		9	1	3163	2805	3615	8	2	>100
and DevNum regs)

Total (without BarOffset	6		3		5	1	2976	2573	3442	8	2	>100
and DevNum regs)	6		3		5	1	2976	2573	3442	8	2	>100
and DevNum regs)

Total (with BarOffset and	4		2		9	1	3181	2851	3667	8	2	>100
DevNum regs)	4		2		9	1	3181	2851	3667	8	2	>100
DevNum regs)

Total (without BarOffset	4		2		9	0	2962	2684	3352	8	2	>100
and DevNum regs)	4		2		9	0	2962	2684	3352	8	2	>100
and DevNum regs)

Notes:

1.These benchmark designs contain only the PLB PCI Bridge with registered inputs/outputs with any additional logic. Benchmark numbers approach the performance ceiling rather that representing performance under typical user conditions.

2.N/A - Not applicable

DS508 March 21, 2006

www.xilinx.com

57

Product Specification

Image 57

Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthBAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision