Xilinx PLB PCI Full Bridge specifications Example

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PLB PCI Full Bridge (v1.00a)

Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a remote PLB address space.

PLB Bus

Note 1

PCI Bus

		BAR_10		BAR_11
PLB PCI Full Bridge
IPIF
C_IPIFBAR_NUM = 3
IPIFBAR_0 IPIFBAR_1		IPIFBAR 2	IPIFBAR 3		IPIFBAR 4	IPIFBAR 5
(high-order	(high-order	(high-order		IPIF to v3.0 LogiCORE Bridge
bit sub)	bit sub)	bit sub)		IPIF to v3.0 LogiCORE Bridge
bit sub)	bit sub)	bit sub)
Addr to PCI	Addr to PCI	Addr to PCI
			Addr to PLB		Addr to PLB
			(high-order		(high-order	Note 2
			(high-order		(high-order
			bit sub)		bit sub)
v3.0 LogiCORE			PCIBAR 0		PCIBAR 1	PCIBAR 2
C_PCIBAR_NUM = 2			PCIBAR 0		PCIBAR 1	PCIBAR 2
C_PCIBAR_NUM = 2

PBAR 20

PBAR 21 PBAR_22

ds508_02_112205

Figure 2: Translation of Addresses Bus-to-Bus with High-Order Bit Substitution

Example 1

Because address translations are performed only when the PLB PCI Bridge is configured with FIFOs, the example shown in Figure 2 is for an PLB PCI Bridge configuration with FIFOs only. In this example, it is assumed that C INCLUDE BAROFFSET REG=0, therefore, the parameters C_IPIFBAR2PCIBAR_N define the high-order bits for substitution in translating the address on the PLB bus to the PCI bus.

The PLB parameters are C IPIFBAR N, C IPIF_HIGHADDR_N, and C_IPIFBAR2PCIBAR_N for N=0 to 5.

The PCI parameters are C_PCIBAR_LEN_M and C_PCIBAR2IPIFBAR_M for M=0 to 2.

Example 2

Example 2 shows of the settings of the two independent sets of base address register (BAR) parameters for specifics of address translation of PLB addresses within the range of a given IPIFBAR to a remote PCI address space. Note that this setting does not depend on the PCIBARs of the PLB PCI Bridge.

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		Product Specification

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Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 CplbawidthIPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code NamePLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busTransaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision