Xilinx PLB PCI Full Bridge Cpcibarnum, CPCIBAR2IPIFBAR0, CPCIBARLEN0, CPCIBAR2IPIFBAR1, Buf

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PLB PCI Full Bridge (v1.00a)

Table 3: PLB PCI Bridge Parameters-Port Dependencies (Contd)

Generic

Parameter

Affects

Depends

Description

 

 

 

 

 

 

 

 

 

The set of PCI/v3.0 BAR-parameters of

 

 

 

 

N = 0 to C_PCIBAR_NUM-1 are

 

 

 

 

meaningful and the parameters of N =

G26

C_PCIBAR_NUM

G27-G32

 

C_PCIBAR_NUM up to and including 2

 

have no effect. If C_PCIBAR_NUM = 3,

 

 

 

 

 

 

 

 

the set of PCI/v3.0 BAR-parameters of N

 

 

 

 

= 0 to 2 are all meaningful (i.e., G27-G32

 

 

 

 

are meaningful)

 

 

 

 

 

G27

C_PCIBAR2IPIFBAR_0

 

G28

Only the high-order bits above the length

 

defined by G28 are meaningful

 

 

 

 

 

 

 

 

 

G28

C_PCIBAR_LEN_0

 

 

 

 

 

 

 

 

 

 

 

 

Only the high-order bits above the length

G29

C_PCIBAR2IPIFBAR_1

 

G30

defined by G30 are meaningful. Not

 

 

 

 

meaningful if G26=1

 

 

 

 

 

G30

C_PCIBAR_LEN_1

 

 

Not meaningful if G26=1

 

 

 

 

 

 

 

 

 

Only the high-order bits above the length

G31

C_PCIBAR2IPIFBAR_2

 

G32

defined by G30 are meaningful. Not

 

 

 

 

meaningful if G26=1-2

 

 

 

 

 

G32

C_PCIBAR_LEN_2

 

 

Not meaningful if G26=1-2

 

 

 

 

 

G33

C_PCI_ABUS_WIDTH

 

 

Only 1 setting

 

 

 

 

 

G34

C_PCI_DBUS_WIDTH

 

 

Only 1 setting

 

 

 

 

 

G35

C_PCI2IPIF_FIFO_ABUS_

 

 

 

WIDTH

 

 

 

 

 

 

 

 

 

 

 

 

G36

C IPIF2PCI FIFO ABUS

 

 

 

WIDTH

 

 

 

 

 

 

 

 

 

 

 

 

G37

C INCLUDE INTR A

P63

 

If G37 = 0, an io-buffer for P63 is not

BUF

 

explicitly instantiated

 

 

 

 

 

 

 

 

G38

C INCLUDE REQ N BUF

P66

 

If G38 = 0, an io-buffer for P66 is not

 

explicitly instantiated

 

 

 

 

 

 

 

 

 

 

 

 

 

Must be set to 5 to the lesser of 24 or the

G39

C TRIG PCI READ OCC

 

G35

PCI2IPIF FIFO DEPTH-1 where the

LEVEL

 

PCI2IPIF FIFO-1 depth is given by

 

 

 

 

 

 

 

2^G35

 

 

 

 

 

 

 

 

 

Must be set to 2 to the lesser of 24 or the

G40

C TRIG IPIF

 

G35

PCI2IPIF FIFO DEPTH-1 where the

WRBURST OCC LEVEL

 

PCI2IPIF FIFO-1 depth is given by

 

 

 

 

 

 

 

2^G35

 

 

 

 

 

 

C_TRIG_PCI_DATA_XFER

 

 

Must be set to 2 to the lesser of 24 or the

G41

 

G36

IPIF2PCI FIFO DEPTH-3 where

_OCC_LEVEL

 

 

 

 

IPIF2PCI FIFO DEPTH given by 2^G36

 

 

 

 

 

 

 

 

 

 

C_TRIG_IPIF_READ_OCC

 

 

Must be set to 1 to the lesser of 24 or the

G42

 

G36

IPIF2PCI FIFO DEPTH-1 where

_LEVEL

 

 

 

 

IPIF2PCI FIFO DEPTH given by 2^G36

 

 

 

 

 

 

 

 

 

20

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DS508 March 21, 2006

 

 

Product Specification

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Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a System Reset Evaluation VersionFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name TYPE2 CIPIFBAR3HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthCPCIBAR2 BARIPIFBAR0 Cplbawidth LEN0PCI2IPIF Fifo Ctrigipif DEPTH-3. PCI2IPIFWrburst Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bus Interface I/O Signals Port Signal Name Interface DescriptionPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Cipifbarnum Ipif BARCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic Cpcibarnum CPCIBAR2IPIFBAR0CPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Command PLB PCI BridgeSupported PCI Bus Commands Code NameRegister Name PLB Address Access PLB PCI Bridge Register DescriptionsPLB PCI Bus Interface Registers Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PCI Initiator Write Serr Enable- Enables this interrupt to PCI Initiator Read Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busPLB PCI Transactions Remote PLB Master PCI I/O Space PCI Memory SpaceTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB SlaveAbnormal condition Memory Read Memory Read Multiple Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History