Xilinx PLB PCI Full Bridge specifications IPIFBAR2PCIBARN High-Order Bits Register Description

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PLB PCI Full Bridge (v1.00a)

bus number. The highest subordinate bus number is also an 8-bit value. The fields are defined in Table 12. Reset clears all bits.

Table 12: Bus Number/Subordinate Bus Number Register Bit Definitions (Bit Assignment Assumes 32-bit

Bus)

Bit(s)

Name

Access

Reset

Description

Value

 

 

 

 

 

 

 

 

 

0-7

D0- D7

Read

0x0

Reserved

 

 

 

 

 

8-15

D8 - D15

Read/Write

0x0

Bus number

 

 

 

 

 

16-23

D16 - D23

Read

0x0

Reserved

 

 

 

 

 

24-31

D24 - D31

Read/Write

0x0

Maximum subordinate bus number

 

 

 

 

 

IPIFBAR2PCIBAR_N High-Order Bits Register Description

When configured to include these registers (i.e., C INCLUDE BAROFFSET REG=1), the values in the registers are used to translate addresses on the PLB bus to the PCI. The register values are used instead of the corresponding parameter C_IPIFBAR2PCIBAR N for translation by high-order bit substitution. The parameters C_IPIFBAR2PCIBAR_N have no effect on the bridge operation if the registers for address translation are included.

The number of registers present is given by the number of IPIF BAR configured in the IPIF (i.e.,

C_IPIFBAR_NUM). The actual width of the Nth register is given by the number of high-order bits that define the complete address range corresponding to the Nth IPIF BAR. When the register is read, 32-bits are returned with the low-order bits hard-wired to zero.

The IPIFBAR2PCIBAR_N registers are included in the bridge via the parameter

C_INCLUDE_BAROFFSET_REG.

These read/write registers allow dynamic, run-time changes of the high-order bits for the substitution in the translation of an address from the PLB bus to the PCI bus. Low-order bits pass directly from the PLB bus to the PCI bus. When the register is read, 32-bits are read with the low-order bits set to zero. Table 13 shows the data format. The programmability of these registers allows PLB address transactions to access any target on the PCI bus which has been arbitrarily assigned a PCI BAR by a remote or local Host Bridge. Dynamic, run-time changes in the high-order bits for address translation of PLB PCI bridge PCI BAR range translation to PLB slaves is not needed because the PLB slave addresses are defined at build time.

Including these registers makes the parameters, C_IPIFBAR2PCIBAR_N, irrelevant because the value in the Nth programmable register replaces the values of the corresponding parameter, C_IPIFBAR2PCIBAR N, in translating the PLB address to the PCI bus. When the registers are included, the parameters, C IPIFBAR2PCIBAR_N, for N=0 to C_IPIFBAR_NUM-1, have no effect.

Table 13: IPIFBAR2PCIBAR N High-Order Bits (Bit assignment assumes 32-bit bus)

Bit(s)

Name

Access

Reset

Description

Value

 

 

 

 

 

 

 

 

 

 

 

 

 

M+1 high-order bits that are substituted in address

0-M

D0 - DM

Read/Write

0x0

translation from Nth IPIFBAR access to PCI address

 

 

 

 

space

 

 

 

 

 

M+1-31

DM+1 - D31

Read Only

0x0

Low-order bits set to zero

 

 

 

 

 

DS508 March 21, 2006

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Product Specification

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Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthBAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB SlaveAbnormal condition Memory Read Memory Read Multiple Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History