Xilinx PLB PCI Full Bridge specifications PLB Master Initiates a Read Request of a PCI target

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PLB PCI Full Bridge (v1.00a)

•Address translations in both directions are performed by high-order address bits substitution in the address vector before crossing to the other bus domain. Byte addressing integrity is maintained between buses.

•The user’s system must be designed to accomodate certain restrictions on throttling by the PLB PCI Bridge. Both PLB and PCI burst transactions may be broken up into multiple transactions on the target or slave bus due to restrictions on bus protocol and modules in the PLB PCI bridge. Additional PLB and PCI transactions are automatically initiated when needed to complete a transaction. The first restriction is that the v3.0 core does not permit throttling of data as either the initiator or target except for insertion of wait states prior to the first data transfer. Another restriction is, that as a master on the PLB, the PLB PCI Bridge is not allowed to throttle, but the PCI remote initiator can cause the need to throttle on the PLB. This is particularly true when the PCI clock is significantly slower than the PLB clock. The PLB PCI Bridge circumvents the throttling limitations by terminating transactions as needed and reinitiating the request to continue as needed. Parameters allow the user to optimize the burst size for high data throughput and minimizing the number of transactions needed to complete the desired burst transactions.

•The interrupt status register in the IPIF contains information to identify an error conditions during the implementation of the PLB PCI bridge and the troubleshooting of the system. To clear the interrupt register bits that were "set" with an error condition, a write of a "1" to the bit position corresponding to the operation must be performed.

•The v3.0 core does not permit throttling of data at either the initiator or target except for insertion of wait states prior to the first data transfer. Consequently, if the PLB device requires throttling that affects the PCI transaction, the PLB PCI Bridge must terminate the transaction. If the v3.0 core is the initiator, a new PCI transaction must be initiated to continue data transfer. Although PLB masters are not allowed to throttle data flow, the combined IPIF and PLB PCI Bridge operation can result in the need for throttling data on the PCI bus, especially when the PLB clock is slower than the PCI clock. The PLB PCI Bridge handles throttling by terminating initiator transactions as needed and continuing the PLB master request with a new PCI transaction. Similarly, new PLB transactions are automatically initiated when needed to complete a PCI initiator transaction.

PLB Master Initiates a Read Request of a PCI target

This section discusses the operation of a PLB master initiating single, burst and cacheline reads of a remote PCI target. In these transactions, the v3.0 core is the PCI initiator.

The operation is similar whether the PCI space is memory or I/O space with the exception of the command sent to the v3.0 core. A parameter associated with each BAR must be consistent with the remote PCI device memory type as either I/O or memory. Based on this parameter setting, either I/O or memory commands are asserted. The PLB IPIF and bridge can accept both fixed length and arbitrary length (i.e., burst length is determined by PLB_rdBurst signal) burst transactions on the PLB. Only one PLB master read of a PCI target is supported at a time.

Commands supported in PLB master read operations are I/O read, memory read, and memory read multiple. The command used is based on the address and qualifier decode, which includes the address, memory type (i.e., I/O or memory type), and if burst is asserted. Table 15 shows translations of PLB transactions to PCI commands.

The address presented on the PLB is translated to the PCI address space by high-order bit substitution with the 2 lsbs set as follows:

• If the target PCI address space is memory space, the 2 lsbs are set to 00 (i.e., linear incrementing

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DS508 March 21, 2006

 

 

Product Specification

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Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a Functional Description System ResetEvaluation Version LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType HIGHADDR3 TYPE2CIPIFBAR3 Cincludebaroff PCIBAR3 CplbawidthIPIFBAR0 Cplbawidth CPCIBAR2BAR LEN0Wrburst PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bridge I/O Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBARHIGHADDR0 CipifbarnumIpif BAR CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBARLEN0 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Supported PCI Bus CommandsCommand PLB PCI Bridge Code NamePLB PCI Bus Interface Registers Register Name PLB Address AccessPLB PCI Bridge Register Descriptions Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Burst Write Retry Timeout Enable- Enables PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busTransaction PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision
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