Xilinx PLB PCI Full Bridge Generic Feature Parameter Allowable Values Default, Description Name

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PLB PCI Full Bridge (v1.00a)

Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields 0xFE35FEDC on the PLB bus.

Table 1: PLB PCI Bridge Interface Design Parameters

Generic

Feature /

Parameter

Allowable Values

Default

VHDL

Description

Name

Value

Type

 

 

 

 

 

 

 

 

 

 

Bridge Features Parameter Group

 

 

 

 

 

 

 

 

 

 

 

1-6; Parameters listed

 

 

 

 

 

below corresponding to

 

 

 

 

 

unused BARs are

 

 

 

 

C_IPIFBAR

ignored, but must be

 

 

G1

Number of IPIF devices

valid values. BAR label

6

integer

_NUM

 

 

0 is the required bar for

 

 

 

 

 

 

 

 

 

 

all values 1-6 and the

 

 

 

 

 

index increments from 0

 

 

 

 

 

as BARs are added

 

 

 

 

 

 

 

 

G2

IPIF device 0 BAR

C_IPIFBAR_0

Valid PLB address (1)

0xFFFFFFFF

std_logic_

 

 

 

 

 

vector

 

 

 

 

 

 

G3

IPIF BAR high address

C_IPIFBAR_

Valid PLB address (1)

0x00000000

std_logic_

 

0

HIGHADDR_0

 

 

vector

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

BAR 0 is mapped

C_IPIFBAR2

Vector of length

 

std_logic_

G4

unless

0xFFFFFFFF

 

C_INCLUDE_BAROFF

PCIBAR_0 1

C PLB AWIDTH

 

vector

 

 

 

 

 

 

SET_REG = 1

 

 

 

 

 

 

 

 

 

 

G5

IPIF BAR 0 memory

C_IPIF_SPACE

0 = I/O space

1

integer

designator

TYPE 0

1 = Memory space

 

 

 

 

 

 

 

 

 

G6

IPIF device 1 BAR

C IPIFBAR_1

Valid PLB address (1)

0xFFFFFFFF

std_logic_

 

 

 

 

 

vector

 

 

 

 

 

 

G7

IPIF BAR high address

C IPIFBAR_

Valid PLB address (1)

0x00000000

std_logic_

 

1

HIGHADDR_1

 

 

vector

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

BAR 1 is mapped

C IPIFBAR2

Vector of length

 

std_logic_

G8

unless

0xFFFFFFFF

 

C INCLUDE BAROFF

PCIBAR 1

C_PLB_AWIDTH

 

vector

 

 

 

 

 

 

SET REG = 1

 

 

 

 

 

 

 

 

 

 

G9

IPIF BAR 1 memory

C IPIF SPACE

0 = I/O space

1

integer

designator

TYPE 1

1 = Memory space

 

 

 

 

 

 

 

 

 

G10

IPIF device 2 BAR

C IPIFBAR_2

Valid PLB address (1)

0xFFFFFFFF

std_logic_

 

 

 

 

 

vector

 

 

 

 

 

 

G11

IPIF BAR high address

C IPIFBAR_

Valid PLB address (1)

0x00000000

std_logic_

 

2

HIGHADDR_2

 

 

vector

 

 

 

 

 

 

 

PCI BAR to which IPIF

 

 

 

 

 

BAR 2 is mapped

 

 

 

 

G12

unless

C_IPIFBAR2

Vector of length

0xFFFFFFFF

std_logic_

 

C_INCLUDE_BAROFF

PCIBAR_2

C_PLB_AWIDTH

 

vector

 

SET_

 

 

 

 

 

REG = 1

 

 

 

 

 

 

 

 

 

 

8

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DS508 March 21, 2006

 

 

Product Specification

Image 8
Contents Introduction LogiCORE FactsFeatures PLB PCI Full Bridge v1.00aPLB PCI Full Bridge v1.00a System Reset Evaluation VersionFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsBus Interface Parameters Address TranslationExample Cpcibar LEN 1=25 Type Generic Feature Parameter Allowable Values DefaultDescription Name TYPE2 CIPIFBAR3HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthCPCIBAR2 BARIPIFBAR0 Cplbawidth LEN0PCI2IPIF Fifo Ctrigipif DEPTH-3. PCI2IPIFWrburst Occlevel 2CPCI2IPIFFIFOAConfiguration V3.0 Core Parameters GroupIpif Parameters Group PLB PCI Bus Interface I/O Signals Port Signal Name Interface DescriptionPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Cipifbarnum Ipif BARCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic Cpcibarnum CPCIBAR2IPIFBAR0CPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Supported PCI Bus Commands Command PLB PCI BridgeSupported PCI Bus Commands Code NameRegister Name PLB Address Access PLB PCI Bridge Register DescriptionsPLB PCI Bus Interface Registers Baseaddr +Register and Parameter Dependencies PLB PCI Bridge Interrupt Registers DescriptionsPLB Master Burst Write Retry Disconnect- Interrupt23 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Timeout- Interrupt22 PCI Initiator Write Serr Enable- Enables this interrupt to PCI Initiator Read Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Bus Number/Subordinate Bus Number Register Description Configuration Address Port Register DescriptionConfiguration Data Port Register Description IPIFBAR2PCIBARN High-Order Bits Register Description CincludebaroffsetregCIPIFSPACETYPE0=1 Host Bridge Device Number Register Description Host Bridge Device Number Bit assignment assumes 32-bit busPLB PCI Transactions Remote PLB Master PCI I/O Space PCI Memory SpaceTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a PLB Master Initiates a Write Request to a PCI Target PerrPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Serr PCI Initiator Initiates a Write Request to a PLB SlaveAbnormal condition Memory Read Memory Read Multiple Abnormal Terminations Configuration Transactions Abnormal condition Memory WriteConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Implementation Design ToolsDesign Debug Design ContraintsNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Target Technology Virtex-4 SupportPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 BRAM# GCLK# Device Utilization and Performance BenchmarksParameter Values Device Resources Date Version Revision Reference DocumentsRevision History