Xilinx PLB PCI Full Bridge specifications Abnormal Terminations

Page 45

PLB PCI Full Bridge (v1.00a)

number of double words are written, the IPIF master burst writes starts after the PCI transaction ends. The bridge attempts to burst write all the data to the PLB slave device.

Although dynamic byte enable is supported on the PCI bus, dynamic byte enable is not supported by the PLB PCI bridge due to the fact that the PLB protocol requires all byte enables to be asserted during burst writes on the PLB. Consequently, it is the user’s responsibility to insure that all byte enables be asserted on the PCI in burst write operations to the PLB PCI bridge.

A PCI initiator can write any number of double words of data in a burst operation to the PLB PCI bridge and the bridge will attempt to burst the data to the PLB slave in a burst write operation on the PLB. The slave may terminate the PLB burst or the FIFO may empty because the FIFO is not filled as fast as the data is transmitted over the PLB.

Only one PCI initiator write to a PLB slave is supported at a time. It is possible for the PLB PCI Bridge to be completing a posted write operation when another write command is received. When this happens, the PLB PCI Bridge will force the v3.0 to disconnect without data until the posted write operation to a remote PLB slave has completed.

A write to a remote slave that is teminated before the FIFO is emptied is automatically retried by the PLB/v3.0 bridge. Address bookkeeping is performed in the IPIF to permit the correct sequence of PLB transactions as either bursts or single transactions and/or combinations of the two as required to complete the transfer.

Abnormal Terminations

•If an address parity error is detected, the v3.0 core will either claim the transaction and issue a target abort, or will not claim the transaction and a master abort will occur (see v3.0 core documentation). If enabled, the v3.0 core asserts SERR N when address phase parity errors are detected.

•If SERR_N is asserted by a remote agent in a data phase, the bridge disconnects without data for burst transfers and the PLB-side PCI Initiator Write SERR interrupt is asserted. If the SERR occurs after the IP master device has started a PLB transaction, the PLB transaction is terminated as soon as possible. The PLB PCI Bridge flushes any data and resets for a subsequent transaction. It is left to the PCI initiator to report the error on the PCI-side and initiate any recovery effort that may be needed.

•If a PERR error is detected on a write transfer, the v3.0 core asserts the PERR signal, if enabled, and sets the Detected PERR error in the status register. The PLB PCI Bridge disconnects without data for burst transfers. On the PLB-side, the bridge terminates the PLB transfer as soon as possible if the transaction is in progress. Due to the latency in PERR, the data for which the PERR was detected most likely has been written to the PLB slave. It is left to the PCI initiator to report the error and initiate any recovery effort that may be needed.

•If at any time while data from the PCI2PLB_FIFO is being written to a PLB slave, a PLB rearbitrate occurs, the PLB PCI Bridge will perform up to a parameterized number of write retries per PCI write command. The parameter C_NUM_IPIF_RETRIES_IN_WRITES will be set at build time and is an independent parameter from the one that sets the number of PCI write retries attempted in PLB Master writes to a PCI target. The wait time between write retries is the PLB arbitration time plus one PLB clock cycle. This is not a parameterized wait time like in the PLB Master to PCI write operation. Furthermore, the PLB PCI Bridge IP master write state machine is tied up during the retry operation, therefore, PCI initiator writes are inhibited. Target disconnects without data (PCI retry) will be asserted for subsequent PCI transactions when the transactions are inhibited.If the

DS508 March 21, 2006

www.xilinx.com

45

Product Specification

Page 44 Page 46
Image 45
Page 44 Page 46
Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a Evaluation Version System ResetFunctional Description LogiCore Version 3.0 32-bit PCI Core RequirementsAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Generic Feature Parameter Allowable Values Default Description NameType CIPIFBAR3 TYPE2HIGHADDR3 Cincludebaroff PCIBAR3 CplbawidthBAR CPCIBAR2IPIFBAR0 Cplbawidth LEN0Ctrigipif DEPTH-3. PCI2IPIF PCI2IPIF FifoWrburst Occlevel 2CPCI2IPIFFIFOAV3.0 Core Parameters Group ConfigurationIpif Parameters Group Port Signal Name Interface Description PLB PCI Bus Interface I/O SignalsPLB PCI Bridge I/O Signals System SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal Ipif BAR CipifbarnumCIPIFBARHIGHADDR0 CIPIFBAR2PCIBAR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR0 CpcibarnumCPCIBARLEN0 CPCIBAR2IPIFBAR1V3.0 Core Parameters Group Command PLB PCI Bridge Supported PCI Bus CommandsSupported PCI Bus Commands Code NamePLB PCI Bridge Register Descriptions Register Name PLB Address AccessPLB PCI Bus Interface Registers Baseaddr +PLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesBits Name Access Reset Description PLB Master Burst Write Retry Timeout- Interrupt22PLB Master Burst Write Retry Disconnect- Interrupt23 PCI Initiator Read Serr Enable- Enables this interrupt to PCI Initiator Write Serr Enable- Enables this interrupt toPLB Master Burst Write Retry Timeout Enable- Enables PLB Master Write Master Abort- Interrupt25 indicatesPLB PCI Bridge Reset Register Description Configuration Address Port Register Description Configuration Data Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionRemote PLB Master PCI I/O Space PCI Memory Space PLB PCI TransactionsTransaction Non-prefetchableTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations PCI Initiator Initiates a Write Request to a PLB Slave Abnormal condition Memory Read Memory Read MultipleSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Device Utilization and Performance Benchmarks Parameter Values Device ResourcesBRAM# GCLK# Reference Documents Revision HistoryDate Version Revision
Top Page Image Contents