Xilinx PLB PCI Full Bridge specifications Host Bridge Device Number Register Description

Page 31

PLB PCI Full Bridge (v1.00a)

Writing 0xFEDC0000 to IPIFBAR2PCIBAR_1 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_1 with address 0xABCDF123 on the PLB bus would yield 0xFEDC1123 on the PCI bus.

Writing 0x40000000 to IPIFBAR2PCIBAR_2 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_2 with address 0xFFFEDCBA on the PLB bus would yield 0x41FEDCBA on the PCI bus.

Writing 0x12345680 to IPIFBAR2PCIBAR_3 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_3 with address 0x0000004A on the PLB bus would yield 0x123456CA on the PCI bus.

Host Bridge Device Number Register Description

The Host Bridge Device Number register is included by setting C_INCLUDE_DEVNUM_REG=1. The register can be included only if configuration functionality is included (i.e., C_INCLUDE_PCI_CONFIG=1).

This register is read/write and is four bits wide. Table 14 shows specifics of the data format. The programmability of this register allows programmable definition of the bridge device number and corresponding address bit that is internally connected to its IDSEL signal. The maximum value that can be loaded in this register is given by the value set by parameter C NUM IDSEL minus 1 because the device number must be consistent with the number of devices that are supported in configuation transactions.

Table 14: Host Bridge Device Number (Bit assignment assumes 32-bit bus)

Bit(s)

Name

Access

Reset

Description

Value

 

 

 

 

 

 

 

 

 

0-27

D0-D27

Read Only

0x0

Set to zero.

 

 

 

 

 

28-31

D28 - D31

Read/Write

0x0

Defines the device number of the PLB PCI bridge when

configured as a Host Bridge.

 

 

 

 

 

 

 

 

 

DS508 March 21, 2006

www.xilinx.com

31

Product Specification

Image 31
Contents LogiCORE Facts IntroductionPLB PCI Full Bridge v1.00a FeaturesPLB PCI Full Bridge v1.00a LogiCore Version 3.0 32-bit PCI Core Requirements System ResetEvaluation Version Functional DescriptionAddress Translation Bus Interface ParametersExample Cpcibar LEN 1=25 Description Name Generic Feature Parameter Allowable Values DefaultType Cincludebaroff PCIBAR3 Cplbawidth TYPE2CIPIFBAR3 HIGHADDR3LEN0 CPCIBAR2BAR IPIFBAR0 CplbawidthOcclevel 2CPCI2IPIFFIFOA PCI2IPIF FifoCtrigipif DEPTH-3. PCI2IPIF WrburstV3.0 Core Parameters Group ConfigurationIpif Parameters Group System Signals PLB PCI Bus Interface I/O SignalsPort Signal Name Interface Description PLB PCI Bridge I/O SignalsPort Signal Name Interface Description Port Signal Name User Asserted PCI Interrupt Signal CIPIFBAR2PCIBAR0 CipifbarnumIpif BAR CIPIFBARHIGHADDR0PLB PCI Bridge Parameters-Port Dependencies Contd Generic CPCIBAR2IPIFBAR1 CpcibarnumCPCIBAR2IPIFBAR0 CPCIBARLEN0V3.0 Core Parameters Group Code Name Supported PCI Bus CommandsCommand PLB PCI Bridge Supported PCI Bus CommandsBaseaddr + Register Name PLB Address AccessPLB PCI Bridge Register Descriptions PLB PCI Bus Interface RegistersPLB PCI Bridge Interrupt Registers Descriptions Register and Parameter DependenciesPLB Master Burst Write Retry Timeout- Interrupt22 Bits Name Access Reset DescriptionPLB Master Burst Write Retry Disconnect- Interrupt23 PLB Master Write Master Abort- Interrupt25 indicates PCI Initiator Write Serr Enable- Enables this interrupt toPCI Initiator Read Serr Enable- Enables this interrupt to PLB Master Burst Write Retry Timeout Enable- EnablesPLB PCI Bridge Reset Register Description Configuration Data Port Register Description Configuration Address Port Register DescriptionBus Number/Subordinate Bus Number Register Description Cincludebaroffsetreg IPIFBAR2PCIBARN High-Order Bits Register DescriptionCIPIFSPACETYPE0=1 Host Bridge Device Number Bit assignment assumes 32-bit bus Host Bridge Device Number Register DescriptionNon-prefetchable PLB PCI TransactionsRemote PLB Master PCI I/O Space PCI Memory Space TransactionTranslation Table for PCI commands to PLB transactions PLB Master Initiates a Read Request of a PCI target Abnormal Terminations PLB PCI Full Bridge v1.00a Perr PLB Master Initiates a Write Request to a PCI TargetPLB PCI Full Bridge v1.00a Abnormal Terminations Write Perr interrupt asserted PCI Initiator Initiates a Read Request of a PLB Slave PLB PCI Full Bridge v1.00a Abnormal Terminations Abnormal condition Memory Read Memory Read Multiple PCI Initiator Initiates a Write Request to a PLB SlaveSerr Abnormal Terminations Abnormal condition Memory Write Configuration TransactionsConfiguration Space Header 0x00 0xFF 0x01 PLB PCI Full Bridge v1.00a Design Tools Design ImplementationDesign Contraints Design DebugNET PCI AD* IOSTANDARD=PCI33 NET PCI CBE* IOSTANDARD=PCI33 Timegrp PCI Pads D OFFSET=IN Virtex-4 Support Target TechnologyPLB PCI Full Bridge v1.00a Parameter CIDELAYCTRLLOC=IDELAYCTRLX2Y5-IDELAYCTRLX2Y6 Parameter Values Device Resources Device Utilization and Performance BenchmarksBRAM# GCLK# Revision History Reference DocumentsDate Version Revision