Agilent Technologies FS2331 user manual Probe Pod Assignment, Pod Clock Domain Clock Rate

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Probe Pod Assignment

The FS2331 DDR Probe uses 8 pods. Two are used to capture traffic on the DDR Command bus, and 6 are used for the Data bus, strobes, check bits, masks, and Serial Presence Detect signals. The signals are mapped to pods as follows:

Pod

Clock Domain

(Clock Rate)

SIGNAL GROUP

 

1 Odd

Data (2x)

State Analysis Clock (on JCLK), DQ0-3, DQ8-11,

 

 

 

DQ16-19, DQS0-2, SA0

 

 

 

 

 

 

 

 

 

 

 

2 Even

Data (2x)

Read/Write status (on KCLK), DQ4-7, DQ12-15,

 

 

 

DQ20-23, DQS9-11, SA1

 

 

 

 

 

 

 

 

 

 

 

3 Odd

Data (2x)

Burst Valid status (on JCLK), CB0-5, DQ24-31,

 

 

 

DQS3, DQS12

 

 

 

 

 

 

 

 

 

 

 

4 Even

Command (1x)

CK0 (on KCLK), A0-15

 

 

 

 

 

 

 

 

Command (1x)

Buffered Command Clock (on JCLK), BA0-2, S0-

 

 

5 Odd

 

3, CKE0-1, WE, RAS, CAS, Reset, FETEN.

 

 

 

 

Spare

 

 

 

 

 

 

 

6 Even

Data (2x)

Buffered Command Clock (on KCLK), CB6-7,

 

 

 

SA2, WP, DQS4, 8, 13, 17. DQ32-39.

 

 

 

 

 

 

 

 

 

 

 

7 Odd

Data (2x)

(Spare – J10on JCLK), SDA, DQS5-7, DQ40-43,

 

 

 

DQ48-51, DQ56-59

 

 

 

 

 

 

 

 

 

 

 

8 Even

Data (2x)

(Spare – J11on JCLK), SCL, DQS14-16, DQ44-

 

 

 

47, DQ52-55, DQ60-63.

 

 

 

 

 

 

 

 

 

 

The overlap in the bit ranges for signals between pods occurs because the bits are assigned to pods in the order that they appear physically on the DIMM connector, which is not strictly in logical bit order. This allows the probe layout to better match stub lengths among all DQxx signals.

See the Appendix for a detailed list of how Logic Analyzer Channels are mapped to signals and DIMM pins.

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportExclusive Remedies Product WarrantyLimitation of warranty Logic Analyzer Modules Probe Cable, Connector NumberingIntroduction DefinitionsFS2331 100 pin Connector to Pod Diagram Probe Components Probe Feature SummaryFS2331 Probe Description DDR Data DDR CommandsProbe Design State Clock GenerationPage Pod Clock Domain Clock Rate Probe Pod AssignmentOn closed Switch # Default factory Function PositionProbe Switch Settings Connecting Power to the FS2331 Probe Logic Analyzer Signal Threshold Voltage SettingsConnecting the Probe to the Logic Analyzer Card Requirements for PC2700 Systems Recommended Logic Analyzer Card Requirements16753/4/5/6 169xx Licensing Setting up the 167xx AnalyzerSetting up the 169xx Analyzer Software Requirements System SoftwareTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Taking a Trace, Triggering, and Seeing Measurement Results Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation State Analysis OperationInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7
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