Agilent Technologies FS2331 user manual Tracing the Serial Presence Detect Signals

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Command and Data analyzers. It can take up to 100ns for the intermodule arm signal to make it from the Command analyzer to the Data analyzer. For this reason it is not possible to guarantee a trigger on a burst at a given address which also has a given data pattern. In general the trigger from the Command/Address analyzer will not be seen by the Data analyzer until the next burst (or an even later one if bursts are less than 100ns apart) occurs.

To set up a trigger, open the trigger tab of the setup window of the Command and Data analyzers, and make adjustments to the default trigger as desired for your measurement.

If the Data analyzer is running in Turbo mode its triggering capabilities will be more limited than the Command analyzer. Also, since the data labels are reordered, range pattern detection will not be available. You can still use store qualification of data within bursts. You can also use flag bits that may be controlled by the command analyzer. If you run into resource limitations when trying to look for a pattern on all data bits, you can usually resolve it by setting a pattern on only 8 or 16 bits in each label, and leaving the rest as “X” (don’t care).

To make a measurement just press the “group run” button and wait for the measurement to complete. Several display windows have been pre-configured to view measurement results with the DDR inverse assembler pre-loaded. The workspace window is a good way to identify each display window and determine which kind of data it displays.

Tracing the Serial Presence Detect Signals

The FS2331 probe can be used along with the Agilent Serial Analysis Tool to decode the Serial Presence Detect lines and view the SPD programming as bytes rather than as serial bits. This is best done by setting the Data module in timing mode and using a slow sample rate about 4x the SPD clock rate.

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportLimitation of warranty Product WarrantyExclusive Remedies Probe Cable, Connector Numbering IntroductionDefinitions Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram FS2331 Probe Description Probe Feature SummaryProbe Components DDR Commands Probe DesignState Clock Generation DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateProbe Switch Settings Switch # Default factory Function PositionOn closed Connecting the Probe to the Logic Analyzer Logic Analyzer Signal Threshold Voltage SettingsConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems 16753/4/5/6 Logic Analyzer Card RequirementsRecommended Setting up the 167xx Analyzer Setting up the 169xx AnalyzerSoftware Requirements System Software 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering Loading the Inverse Assembler and Decoding DDR Commands Timing Analysis OperationState Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7
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