Agilent Technologies user manual Using EyeScan with the FS2331 Probe

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Using EyeScan with the FS2331 Probe

EyeScan is a feature available on Agilent 16760 and 16753/4/5/6 logic analyzer cards. It provides the ability to perform eye measurements on multiple channels simultaneously. For more detailed information on the use of the feature refer to the Help files for either logic analyzer. Several points to bear in mind when using EyeScan with the FS2331 DDR DIMM probe are:

1.You cannot run EyeScan on the signal being used as a clock to the logic analyzer. This makes it impossible to view Data Clk, and either CK0 or Buffered Command Clk depending on the setup of the Command Analyzer.

2.Because Data Clk and Buffered Command Clock are signals that are created by the probe, they are delayed relative to other DDR DIMM signals when received at the logic analyzer. This means that when using these signals as clocks the valid eye diagrams seen are actually to the left of the centerpoint of the display.

3.It may be more effective to get satisfactory Eye Finder results first and then move onto using EyeScan. It is also faster to do the first EyeScan measurements on just a few channels to insure that the voltage, timebase and screen settings are satisfactory before running an EyeScan on a large group of signals.

Here is an example EyeScan measurement of a DQ signal taken on a DDR333 bus using the FS2331 probe:

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Contents DDR Sdram Analysis Probe FS2331 RevisionHow to reach us Product Warranty Signal Connections For Technical Support For Sales and Marketing SupportProduct Warranty Limitation of warrantyExclusive Remedies Definitions Probe Cable, Connector NumberingIntroduction Logic Analyzer ModulesFS2331 100 pin Connector to Pod Diagram Probe Feature Summary FS2331 Probe DescriptionProbe Components State Clock Generation DDR CommandsProbe Design DDR DataPage Probe Pod Assignment Pod Clock Domain Clock RateSwitch # Default factory Function Position Probe Switch SettingsOn closed Logic Analyzer Signal Threshold Voltage Settings Connecting the Probe to the Logic AnalyzerConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems Logic Analyzer Card Requirements 16753/4/5/6Recommended Software Requirements System Software Setting up the 167xx AnalyzerSetting up the 169xx Analyzer 169xx LicensingTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory Connecting to your Target System Chip Select If User is dedicating aChip Select Jumper locations § Isolate the Dedicated DIMM’s pin§ Sleeve the Pin § Wire from the adjacent Dimm slot to the isolated pin Unused PodsOffline Analysis Filtering State Analysis Operation Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation Taking a Trace, Triggering, and Seeing Measurement ResultsInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Using the FS2331 DDR Probe with an Interposer FS1024/25 Dimm Signal Loading OptionFS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Adjust the delay line value to maximize R/W overlap Set the final analyzer sample positionPage General Information Standards supportedSignal Connections J1 Data SamtecSA0 J2 Data and Command CB4Spare J3 Command and Data Buffcmdclk J4 Data DM5DQS14DQS7