Agilent Technologies FS2331 user manual

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The read strobes straddle the data, as they should for read cycles.

The read data valid windows are about the same size as the write ones were. In many systems however you should not be surprised to find the read windows appreciably smaller than the write windows. This is due to the physics of the DDR bus. For read data the analyzer must typically wait for the reflected wave (created by the DRAM and reflected by the controller chipset) to determine when strobes and data actually switch. As a result the waveforms are usually much less clean. This results in an increased amount of jitter in the detected strobe and the data itself. This shows up as a smaller data valid window for the sampled data. The FS2331 probe incorporates special circuitry and techniques to deal with this as effectively as possible Because of these signal integrity challenges however the probe may not be able to reliably capture read bursts under all conditions. The Eye Finder measurements will tell you which bits may have trouble being sampled most reliably.

These DIMMs apparently use x8 memories since there is no stable data on the mask/upper strobe lines. Although there is special circuitry on the probe to deal with the high impedance state on the DQS0 strobe (which generates the state analysis clock), the other lines simply sample data using a threshold of 1.25 volts. As a result when lines are tristated continuously (and so get pulled to the threshold by the terminators) the analyzer will interpret even small amounts of noise as random 0/1 transitions.

As with write bursts, if Eye Finder chooses the wrong data valid window when selecting the sample position, move the sample positions to the proper one (just before the analyzer clock at time 0) before noting the average sample position indicated for the data lines. After adjusting the sample positions you should see a display like the following:

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Contents Revision DDR Sdram Analysis Probe FS2331How to reach us Product Warranty Signal Connections For Sales and Marketing Support For Technical SupportLimitation of warranty Product WarrantyExclusive Remedies Logic Analyzer Modules Probe Cable, Connector NumberingIntroduction DefinitionsFS2331 100 pin Connector to Pod Diagram FS2331 Probe Description Probe Feature SummaryProbe Components DDR Data DDR CommandsProbe Design State Clock GenerationPage Pod Clock Domain Clock Rate Probe Pod AssignmentProbe Switch Settings Switch # Default factory Function PositionOn closed Connecting the Probe to the Logic Analyzer Logic Analyzer Signal Threshold Voltage SettingsConnecting Power to the FS2331 Probe Card Requirements for PC2700 Systems 16753/4/5/6 Logic Analyzer Card RequirementsRecommended 169xx Licensing Setting up the 167xx AnalyzerSetting up the 169xx Analyzer Software Requirements System SoftwareTiming Analysis All DDR speeds and supported analyzer cards Card Configurations for State Analysis Probing multiple DDR busses Interleaved memory If User is dedicating a Connecting to your Target System Chip Select§ Isolate the Dedicated DIMM’s pin Chip Select Jumper locations§ Sleeve the Pin Unused Pods § Wire from the adjacent Dimm slot to the isolated pinOffline Analysis Filtering Taking a Trace, Triggering, and Seeing Measurement Results Loading the Inverse Assembler and Decoding DDR CommandsTiming Analysis Operation State Analysis OperationInverse Assembler and Decoding DDR Commands Tracing the Serial Presence Detect Signals Using Eye Finder with the FS2331 DDR Probe Using EyeScan with the FS2331 Probe Dimm Signal Loading Option Using the FS2331 DDR Probe with an Interposer FS1024/25FS2331 Calibration Page Set Command sample position Page Page Write Burst Data Valid Position Page Page Page Read Burst Data Valid Position Page Page Page Set the final analyzer sample position Adjust the delay line value to maximize R/W overlapPage Standards supported General InformationSamtec Signal Connections J1 DataSA0 CB4 J2 Data and CommandSpare J3 Command and Data Buffcmdclk DM5DQS14 J4 DataDQS7